val = le_readl(reg);
if ((val & mask) == result)
break;
- msleep(10);
if (t >= max_ms) {
- dev_err(dev, "timed out waiting for %s ", tag);
+ dev_err(dev, "%s timed out\n", tag);
return -ETIMEDOUT;
}
+ msleep(10);
t += 10;
}
return 0;
+ UWBCAPDATA_TO_OFFSET(capdata);
umc->resource.end = umc->resource.start
+ (n == 0 ? 0x20 : UWBCAPDATA_TO_SIZE(capdata)) - 1;
- umc->resource.name = umc->dev.bus_id;
+ umc->resource.name = dev_name(&umc->dev);
umc->resource.flags = card->pci->resource[bar].flags;
umc->resource.parent = &card->pci->resource[bar];
umc->irq = card->pci->irq;
pci_enable_msi(pci);
pci_set_master(pci);
err = -ENXIO;
- if (!pci_set_dma_mask(pci, DMA_64BIT_MASK))
- pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
- else if (!pci_set_dma_mask(pci, DMA_32BIT_MASK))
- pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
+ if (!pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
+ pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
+ else if (!pci_set_dma_mask(pci, DMA_BIT_MASK(32)))
+ pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
else
goto error_dma;