#include "r8192S_phy.h"
#include "r8192S_phyreg.h"
#include "r8192SU_HWImg.h"
-//#include "r8192S_FwImgDTM.h"
#include "ieee80211/dot11d.h"
}
/**
-* Function: phy_RFSerialRead
-*
-* OverView: Read regster from RF chips
-*
-* Input:
-* PADAPTER Adapter,
-* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
-* u4Byte Offset, //The target address to be read
-*
-* Output: None
-* Return: u4Byte reback value
-* Note: Threre are three types of serial operations:
-* 1. Software serial write
-* 2. Hardware LSSI-Low Speed Serial Interface
-* 3. Hardware HSSI-High speed
-* serial write. Driver need to implement (1) and (2).
-* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
-*/
-#if 0
-static u32
-phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
-{
-
- u32 retValue = 0;
- struct r8192_priv *priv = ieee80211_priv(dev);
- BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
- u32 NewOffset;
- //u32 value = 0;
- u32 tmplong,tmplong2;
- u32 RfPiEnable=0;
-#if 0
- if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
- return retValue;
- if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
- return retValue;
-#endif
- //
- // Make sure RF register offset is correct
- //
- Offset &= 0x3f;
-
- //
- // Switch page for 8256 RF IC
- //
- NewOffset = Offset;
-
- // For 92S LSSI Read RFLSSIRead
- // For RF A/B write 0x824/82c(does not work in the future)
- // We must use 0x824 for RF A and B to execute read trigger
- tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
- tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
- tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
-
- rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
- mdelay(1);
-
- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
- mdelay(1);
-
- rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
- mdelay(1);
-
- if(eRFPath == RF90_PATH_A)
- RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
- else if(eRFPath == RF90_PATH_B)
- RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
-
- if(RfPiEnable)
- { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
- retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
- //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
- }
- else
- { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
- retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
- //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
- }
- //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
-
- return retValue;
-
-}
-4
-
-
-/**
-* Function: phy_RFSerialWrite
-*
-* OverView: Write data to RF register (page 8~)
-*
-* Input:
-* PADAPTER Adapter,
-* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
-* u4Byte Offset, //The target address to be read
-* u4Byte Data //The new register Data in the target bit position
-* //of the target to be read
-*
-* Output: None
-* Return: None
-* Note: Threre are three types of serial operations:
-* 1. Software serial write
-* 2. Hardware LSSI-Low Speed Serial Interface
-* 3. Hardware HSSI-High speed
-* serial write. Driver need to implement (1) and (2).
-* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
- *
- * Note: For RF8256 only
- * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
- * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
- * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
- * programming guide" for more details.
- * Thus, we define a sub-finction for RTL8526 register address conversion
- * ===========================================================
- * Register Mode RegCTL[1] RegCTL[0] Note
- * (Reg00[12]) (Reg00[10])
- * ===========================================================
- * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
- * ------------------------------------------------------------------
- * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
- * ------------------------------------------------------------------
- * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
- * ------------------------------------------------------------------
- *
- * 2008/09/02 MH Add 92S RF definition
- *
- *
- *
-*/
-static void
-phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data)
-{
- u32 DataAndAddr = 0;
- struct r8192_priv *priv = ieee80211_priv(dev);
- BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
- u32 NewOffset;
-
-#if 0
- //<Roger_TODO> We should check valid regs for RF_6052 case.
- if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
- return;
- if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
- return;
-#endif
-
- Offset &= 0x3f;
-
- //
- // Shadow Update
- //
- PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
-
- //
- // Switch page for 8256 RF IC
- //
- NewOffset = Offset;
-
- //
- // Put write addr in [5:0] and write data in [31:16]
- //
- //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
- DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
-
- //
- // Write Operation
- //
- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
- //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
-
-}
-#endif
-
-/**
* Function: phy_CalculateBitShift
*
* OverView: Get shifted position of the BitMask
//
// 1. Read PHY_REG.TXT BB INIT!!
- // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
+ // We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R
//
if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
}
-#if 0 // 2008/08/18 MH Disable for 92SE
- if(pHalData->VersionID > VERSION_8190_BD)
- {
- //if(pHalData->RF_Type == RF_2T4R)
- //{
- // Antenna gain offset from B/C/D to A
- u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 |
- pHalData->AntennaTxPwDiff[1]<<4 |
- pHalData->AntennaTxPwDiff[0]);
- //}
- //else
- //u4RegValue = 0;
-
- PHY_SetBBReg(dev, rFPGA0_TxGainStage,
- (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
-
- // CrystalCap
- // Simulate 8192???
- u4RegValue = pHalData->CrystalCap;
- PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
- // Simulate 8190??
- //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
- //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
-
- }
-#endif
-
// Check if the CCK HighPower is turned ON.
// This is used to calculate PWDB.
priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
case eRfOff:
if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
break;
-#ifdef NOT_YET
- // Make sure BusyQueue is empty befor turn off RFE pwoer.
- for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
- {
- if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
- {
- QueueID++;
- continue;
- }
- else
- {
- RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
- udelay(10);
- i++;
- }
-
- if(i >= MAX_DOZE_WAITING_TIMES_9x)
- {
- RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
- break;
- }
- }
-#endif
//
//RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
// Added by Bruce, 2008-11-22.
default:
bResult = FALSE;
- //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
+ //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknown state to set: 0x%X!!!\n", eRFPowerState));
break;
}
break;
if(priv->bTXPowerDataReadFromEEPORM == FALSE)
return;
- //
- // Read predefined TX power index in EEPROM
- //
-// if(priv->epromtype == EPROM_93c46)
+ /*
+ * Read predefined TX power index in EEPROM
+ */
{
//
// Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
// Calculate Antenna pwr diff
if (pwrdiff[rfpath] < 8) // 0~+7
{
- #if 0//cosa, it doesn't need to add the offset here
- if (rfpath == 0)
- powerlevelOFDM24G += pwrdiff[rfpath];
- #endif
ht20pwr[rfpath] += pwrdiff[rfpath];
}
else // index8-15=-8~-1
{
- #if 0//cosa, it doesn't need to add the offset here
- if (rfpath == 0)
- powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
- #endif
ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
}
}
ht20pwr[rfpath] -= pwrdiff[rfpath];
}
- #if 0//cosa, it doesn't need to add the offset here
- if (rfpath == 0)
- powerlevelOFDM24G -= pwrdiff[rfpath];
- #endif
}
if (priv->rf_type == RF_2T2R)
}
}
}
-#if 0//cosa, useless
- // Read HT/Legacy OFDM diff
- legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
-#endif
}
//Cosa added for protection, the reg rFPGA0_TxGainStage
break;
case RF_8256:
-#if 0
- PHY_SetRF8256CCKTxPower(dev, powerlevel);
- PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
-#endif
break;
case RF_6052:
//struct r8192_priv *priv = ieee80211_priv(dev);
//u32 BitMask;
//u8 initial_gain;
-
-#if 0 // For 8192s test disable
- if(!dev->bDriverStopped)
- {
- switch(Operation)
- {
- case IG_Backup:
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
- initial_gain = priv->DefaultInitialGain[0];
- BitMask = bMaskByte0;
- if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
- PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
- pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
- pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
- pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
- pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
- BitMask = bMaskByte2;
- pMgntInfo->InitGain_Backup.CCA = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
-
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
-
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
- write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
- write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
- break;
- case IG_Restore:
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
- BitMask = 0x7f; //Bit0~ Bit6
- if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
- PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
-
- rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
- rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
- rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
- rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
- BitMask = (BIT22|BIT23);
- rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
-
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
-
- if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
- PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
- break;
- default:
- RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
- break;
- }
- }
-#endif
}
/*-----------------------------------------------------------------------------
break;
default:
- RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
- unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
+ RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n",
+ priv->CurrentChannelBW);
break;
}
//write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
//write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
- #if 0 //LZM 090219
- rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
- rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
- rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
- #endif
if (priv->card_8192_version >= VERSION_8192S_BCUT)
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
//write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
//write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
- #if 0 //LZM 090219
- rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
- rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
- rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
- #endif
// Set Control channel to upper or lower. These settings are required only for 40MHz
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
else
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-#if 0
- if(!priv->bDriverStopped)
- {
-#ifdef USE_WORKITEM
- PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
-#else
- PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
-#endif
- }
-#endif
if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
{
SetBWModeCallback8192SUsbWorkItem(dev);
// However, this procedure is performed synchronously which should be running under
// passive level.
//
-//not understant it
+//not understand it
void PHY_SwChnlPhy8192S( // Only called during initialize
struct net_device* dev,
u8 channel
bool rtValue = TRUE;
// NOt check RF Path now.!
-#if 0
- if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
- {
- rtValue = FALSE;
- }
- if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
- {
-
- }
-#endif
return rtValue;
} /* PHY_CheckIsLegalRfPath8192S */
u32 delay;
// bool ret;
- RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
- %d\n", priv->chan);
+ RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel %d\n",
+ priv->chan);
if(!priv->up)
break;
default:
- RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
- unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
+ RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n",
+ priv->CurrentChannelBW);
break;
}
case HT_CHANNEL_WIDTH_20:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
- #if 0 //LZM090219
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
-
- // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
- //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
- //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
- //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
- rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
- rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
- rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
- #endif
if (priv->card_8192_version >= VERSION_8192S_BCUT)
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
}
-//
-// Callback routine of the work item for set bandwidth mode.
-//
-// use in phy only (in win it's work)
+/*
+ * Callback routine of the work item for set bandwidth mode.
+ *
+ * use in phy only (in win it's work)
+ */
void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
{
- struct r8192_priv *priv = ieee80211_priv(dev);
- u8 regBwOpMode;
-
- // Added it for 20/40 mhz switch time evaluation by guangan 070531
- //u32 NowL, NowH;
- //u8Byte BeginTime, EndTime;
- u8 regRRSR_RSC;
+ struct r8192_priv *priv = ieee80211_priv(dev);
+ u8 regBwOpMode;
+ u8 regRRSR_RSC;
- RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem() Switch to %s bandwidth\n", \
- priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
+ RT_TRACE(COMP_SCAN, "%s(): Switch to %s bandwidth", __func__,
+ priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz");
- if(priv->rf_chip == RF_PSEUDO_11N)
- {
+ if (priv->rf_chip == RF_PSEUDO_11N) {
priv->SetBWModeInProgress= FALSE;
return;
}
-
if(!priv->up)
return;
-
- // Added it for 20/40 mhz switch time evaluation by guangan 070531
- //NowL = read_nic_dword(dev, TSFR);
- //NowH = read_nic_dword(dev, TSFR+4);
- //BeginTime = ((u8Byte)NowH << 32) + NowL;
-
- //3<1>Set MAC register
+ /* Set MAC register */
regBwOpMode = read_nic_byte(dev, BW_OPMODE);
regRRSR_RSC = read_nic_byte(dev, RRSR+2);
-
- switch(priv->CurrentChannelBW)
- {
- case HT_CHANNEL_WIDTH_20:
- regBwOpMode |= BW_OPMODE_20MHZ;
- // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
- break;
-
- case HT_CHANNEL_WIDTH_20_40:
- regBwOpMode &= ~BW_OPMODE_20MHZ;
- // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
- regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
- write_nic_byte(dev, RRSR+2, regRRSR_RSC);
-
- break;
-
- default:
- RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
- unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
- break;
+ switch (priv->CurrentChannelBW) {
+ case HT_CHANNEL_WIDTH_20:
+ regBwOpMode |= BW_OPMODE_20MHZ;
+ /* we have not verified whether this register works */
+ write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ break;
+ case HT_CHANNEL_WIDTH_20_40:
+ regBwOpMode &= ~BW_OPMODE_20MHZ;
+ /* we have not verified whether this register works */
+ write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ regRRSR_RSC = (regRRSR_RSC&0x90) | (priv->nCur40MhzPrimeSC<<5);
+ write_nic_byte(dev, RRSR+2, regRRSR_RSC);
+ break;
+ default:
+ RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
+ priv->CurrentChannelBW);
+ break;
}
-
- //3 <2>Set PHY related register
- switch(priv->CurrentChannelBW)
- {
- case HT_CHANNEL_WIDTH_20:
- rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
- rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
-
- #if 0 //LZM 090219
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
-
- // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
- rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
- rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
- rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
- #endif
-
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
-
- break;
- case HT_CHANNEL_WIDTH_20_40:
- rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
- rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
- #if 0 //LZM 090219
- rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
-
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
-
- rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
- // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
- rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
- rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
- rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
- #endif
-
- // Set Control channel to upper or lower. These settings are required only for 40MHz
- rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
- rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
-
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
-
- break;
-
-
- default:
- RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
- ,priv->CurrentChannelBW);
- break;
+ /* Set PHY related register */
+ switch (priv->CurrentChannelBW) {
+ case HT_CHANNEL_WIDTH_20:
+ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
+ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
+ break;
+ case HT_CHANNEL_WIDTH_20_40:
+ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
+ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
+ /*
+ * Set Control channel to upper or lower.
+ * These settings are required only for 40MHz
+ */
+ rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
+ (priv->nCur40MhzPrimeSC>>1));
+ rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
+ priv->nCur40MhzPrimeSC);
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
+ break;
+ default:
+ RT_TRACE(COMP_DBG, "%s(): unknown Bandwidth: %#X", __func__,
+ priv->CurrentChannelBW);
+ break;
}
- //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
-
- //3<3>Set RF related register
- switch( priv->rf_chip )
- {
- case RF_8225:
- PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
- break;
-
- case RF_8256:
- // Please implement this function in Hal8190PciPhy8256.c
- //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
- break;
-
- case RF_6052:
- PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
- break;
-
- case RF_8258:
- // Please implement this function in Hal8190PciPhy8258.c
- // PHY_SetRF8258Bandwidth();
- break;
-
- case RF_PSEUDO_11N:
- // Do Nothing
- break;
+ /*
+ * Skip over setting of J-mode in BB register here.
+ * Default value is "None J mode".
+ */
- default:
- //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
- break;
+ /* Set RF related register */
+ switch (priv->rf_chip) {
+ case RF_8225:
+ PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
+ break;
+ case RF_8256:
+ /* Please implement this function in Hal8190PciPhy8256.c */
+ /* PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); */
+ break;
+ case RF_6052:
+ PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
+ break;
+ case RF_8258:
+ /* Please implement this function in Hal8190PciPhy8258.c */
+ /* PHY_SetRF8258Bandwidth(); */
+ break;
+ case RF_PSEUDO_11N:
+ /* Do Nothing */
+ break;
+ default:
+ RT_TRACE(COMP_DBG, "%s(): unknown rf_chip: %d", __func__,
+ priv->rf_chip);
+ break;
}
-
priv->SetBWModeInProgress= FALSE;
-
- RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
}
//--------------------------Move to oter DIR later-------------------------------*/
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff