unsigned char *p;
unsigned int count;
struct uart_port *port = &qe_port->port;
- struct circ_buf *xmit = &port->info->xmit;
+ struct circ_buf *xmit = &port->state->xmit;
bdp = qe_port->rx_cur;
int i;
unsigned char ch, *cp;
struct uart_port *port = &qe_port->port;
- struct tty_struct *tty = port->info->port.tty;
+ struct tty_struct *tty = port->state->port.tty;
struct qe_bd *bdp;
u16 status;
unsigned int flg;
out_be16(&uccup->rccm, 0xc0ff);
/* Configure the GUMR registers for UART */
- if (soft_uart)
+ if (soft_uart) {
/* Soft-UART requires a 1X multiplier for TX */
clrsetbits_be32(&uccp->gumr_l,
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
UCC_SLOW_GUMR_L_RDCR_MASK,
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
UCC_SLOW_GUMR_L_RDCR_16);
- else
+
+ clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+ } else {
clrsetbits_be32(&uccp->gumr_l,
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
UCC_SLOW_GUMR_L_RDCR_MASK,
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
UCC_SLOW_GUMR_L_RDCR_16);
- clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
- UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+ clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
+ UCC_SLOW_GUMR_H_RFW);
+ }
#ifdef LOOPBACK
clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
UCC_SLOW_GUMR_H_CDS);
#endif
- /* Enable rx interrupts and clear all pending events. */
+ /* Disable rx interrupts and clear all pending events. */
out_be16(&uccp->uccm, 0);
out_be16(&uccp->ucce, 0xffff);
out_be16(&uccp->udsr, 0x7e7e);
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
QE_CR_PROTOCOL_UNSPECIFIED, 0);
+ } else {
+ cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
+ QE_CR_PROTOCOL_UART, 0);
}
}
rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
- bd_virt = dma_alloc_coherent(NULL, rx_size + tx_size, &bd_dma_addr,
+ bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
GFP_KERNEL);
if (!bd_virt) {
dev_err(port->dev, "could not allocate buffer descriptors\n");
container_of(port, struct uart_qe_port, port);
struct ucc_slow_private *uccs = qe_port->us_private;
- dma_free_coherent(NULL, qe_port->bd_size, qe_port->bd_virt,
+ dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
qe_port->bd_dma_addr);
ucc_slow_free(uccs);
if (!iprop) {
iprop = of_get_property(np, "device-id", NULL);
if (!iprop) {
+ kfree(qe_port);
dev_err(&ofdev->dev, "UCC is unspecified in "
"device tree\n");
return -EINVAL;