[S390] cio: Remove CCW_CMD_SUSPEND_RECONN in front of CCW_CMD_SET_PGID.

[safe/jmp/linux-2.6] / drivers / pci / setup-bus.c

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index d4f4c12..8ddb918 100644 (file)
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -145,8 +145,7 @@ EXPORT_SYMBOL(pci_setup_cardbus);
    config space writes, so it's quite possible that an I/O window of
    the bridge will have some undesirable address (e.g. 0) after the
    first write. Ditto 64-bit prefetchable MMIO.  */
-static void __devinit
-pci_setup_bridge(struct pci_bus *bus)
+static void pci_setup_bridge(struct pci_bus *bus)
 {
        struct pci_dev *bridge = bus->self;
        struct pci_bus_region region;
@@ -417,13 +416,13 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
         * Reserve some resources for CardBus.  We reserve
         * a fixed amount of bus space for CardBus bridges.
         */
-       b_res[0].start = pci_cardbus_io_size;
-       b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
-       b_res[0].flags |= IORESOURCE_IO;
+       b_res[0].start = 0;
+       b_res[0].end = pci_cardbus_io_size - 1;
+       b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
 
-       b_res[1].start = pci_cardbus_io_size;
-       b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
-       b_res[1].flags |= IORESOURCE_IO;
+       b_res[1].start = 0;
+       b_res[1].end = pci_cardbus_io_size - 1;
+       b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
 
        /*
         * Check whether prefetchable memory is supported
@@ -442,17 +441,17 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
         * twice the size.
         */
        if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
-               b_res[2].start = pci_cardbus_mem_size;
-               b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
-               b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
+               b_res[2].start = 0;
+               b_res[2].end = pci_cardbus_mem_size - 1;
+               b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
 
-               b_res[3].start = pci_cardbus_mem_size;
-               b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
-               b_res[3].flags |= IORESOURCE_MEM;
+               b_res[3].start = 0;
+               b_res[3].end = pci_cardbus_mem_size - 1;
+               b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
        } else {
-               b_res[3].start = pci_cardbus_mem_size * 2;
-               b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
-               b_res[3].flags |= IORESOURCE_MEM;
+               b_res[3].start = 0;
+               b_res[3].end = pci_cardbus_mem_size * 2 - 1;
+               b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
        }
 }