ixgbe: Cleanup incorrect header comments

[safe/jmp/linux-2.6] / drivers / pci / pci.c

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 930eadf..315fea4 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -29,7 +29,17 @@ const char *pci_power_names[] = {
 };
 EXPORT_SYMBOL_GPL(pci_power_names);
 
-unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
+unsigned int pci_pm_d3_delay;
+
+static void pci_dev_d3_sleep(struct pci_dev *dev)
+{
+       unsigned int delay = dev->d3_delay;
+
+       if (delay < pci_pm_d3_delay)
+               delay = pci_pm_d3_delay;
+
+       msleep(delay);
+}
 
 #ifdef CONFIG_PCI_DOMAINS
 int pci_domains_supported = 1;
@@ -382,8 +392,12 @@ pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
                        continue;       /* Wrong type */
                if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
                        return r;       /* Exact match */
-               if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
-                       best = r;       /* Approximating prefetchable by non-prefetchable */
+               /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
+               if (r->flags & IORESOURCE_PREFETCH)
+                       continue;
+               /* .. but we can put a prefetchable resource inside a non-prefetchable one */
+               if (!best)
+                       best = r;
        }
        return best;
 }
@@ -518,7 +532,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
        /* Mandatory power management transition delays */
        /* see PCI PM 1.1 5.6.1 table 18 */
        if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
-               msleep(pci_pm_d3_delay);
+               pci_dev_d3_sleep(dev);
        else if (state == PCI_D2 || dev->current_state == PCI_D2)
                udelay(PCI_PM_D2_DELAY);
 
@@ -737,8 +751,8 @@ static int pci_save_pcie_state(struct pci_dev *dev)
        u16 *cap;
        u16 flags;
 
-       pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-       if (pos <= 0)
+       pos = pci_pcie_cap(dev);
+       if (!pos)
                return 0;
 
        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
@@ -846,7 +860,7 @@ pci_save_state(struct pci_dev *dev)
        int i;
        /* XXX: 100% dword access ok here? */
        for (i = 0; i < 16; i++)
-               pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
+               pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
        dev->state_saved = true;
        if ((i = pci_save_pcie_state(dev)) != 0)
                return i;
@@ -1149,11 +1163,11 @@ pci_disable_device(struct pci_dev *dev)
 
 /**
  * pcibios_set_pcie_reset_state - set reset state for device dev
- * @dev: the PCI-E device reset
+ * @dev: the PCIe device reset
  * @state: Reset state to enter into
  *
  *
- * Sets the PCI-E reset state for the device. This is the default
+ * Sets the PCIe reset state for the device. This is the default
  * implementation. Architecture implementations can override this.
  */
 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
@@ -1164,7 +1178,7 @@ int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
 
 /**
  * pci_set_pcie_reset_state - set reset state for device dev
- * @dev: the PCI-E device reset
+ * @dev: the PCIe device reset
  * @state: Reset state to enter into
  *
  *
@@ -1405,6 +1419,7 @@ void pci_pm_init(struct pci_dev *dev)
        }
 
        dev->pm_cap = pm;
+       dev->d3_delay = PCI_PM_D3_WAIT;
 
        dev->d1_support = false;
        dev->d2_support = false;
@@ -1520,7 +1535,7 @@ void pci_enable_ari(struct pci_dev *dev)
        u16 ctrl;
        struct pci_dev *bridge;
 
-       if (!dev->is_pcie || dev->devfn)
+       if (!pci_is_pcie(dev) || dev->devfn)
                return;
 
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
@@ -1528,10 +1543,10 @@ void pci_enable_ari(struct pci_dev *dev)
                return;
 
        bridge = dev->bus->self;
-       if (!bridge || !bridge->is_pcie)
+       if (!bridge || !pci_is_pcie(bridge))
                return;
 
-       pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
+       pos = pci_pcie_cap(bridge);
        if (!pos)
                return;
 
@@ -1546,6 +1561,16 @@ void pci_enable_ari(struct pci_dev *dev)
        bridge->ari_enabled = 1;
 }
 
+static int pci_acs_enable;
+
+/**
+ * pci_request_acs - ask for ACS to be enabled if supported
+ */
+void pci_request_acs(void)
+{
+       pci_acs_enable = 1;
+}
+
 /**
  * pci_enable_acs - enable ACS if hardware support it
  * @dev: the PCI device
@@ -1556,7 +1581,10 @@ void pci_enable_acs(struct pci_dev *dev)
        u16 cap;
        u16 ctrl;
 
-       if (!dev->is_pcie)
+       if (!pci_acs_enable)
+               return;
+
+       if (!pci_is_pcie(dev))
                return;
 
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
@@ -2097,6 +2125,7 @@ pci_set_dma_mask(struct pci_dev *dev, u64 mask)
                return -EIO;
 
        dev->dma_mask = mask;
+       dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
 
        return 0;
 }
@@ -2108,6 +2137,7 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
                return -EIO;
 
        dev->dev.coherent_dma_mask = mask;
+       dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
 
        return 0;
 }
@@ -2134,9 +2164,9 @@ static int pcie_flr(struct pci_dev *dev, int probe)
        int i;
        int pos;
        u32 cap;
-       u16 status;
+       u16 status, control;
 
-       pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+       pos = pci_pcie_cap(dev);
        if (!pos)
                return -ENOTTY;
 
@@ -2161,8 +2191,10 @@ static int pcie_flr(struct pci_dev *dev, int probe)
                        "proceeding with reset anyway\n");
 
 clear:
-       pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
-                               PCI_EXP_DEVCTL_BCR_FLR);
+       pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
+       control |= PCI_EXP_DEVCTL_BCR_FLR;
+       pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
+
        msleep(100);
 
        return 0;
@@ -2226,12 +2258,12 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
        csr &= ~PCI_PM_CTRL_STATE_MASK;
        csr |= PCI_D3hot;
        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-       msleep(pci_pm_d3_delay);
+       pci_dev_d3_sleep(dev);
 
        csr &= ~PCI_PM_CTRL_STATE_MASK;
        csr |= PCI_D0;
        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-       msleep(pci_pm_d3_delay);
+       pci_dev_d3_sleep(dev);
 
        return 0;
 }
@@ -2275,6 +2307,10 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
                down(&dev->dev.sem);
        }
 
+       rc = pci_dev_specific_reset(dev, probe);
+       if (rc != -ENOTTY)
+               goto done;
+
        rc = pcie_flr(dev, probe);
        if (rc != -ENOTTY)
                goto done;
@@ -2485,7 +2521,7 @@ int pcie_get_readrq(struct pci_dev *dev)
        int ret, cap;
        u16 ctl;
 
-       cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
+       cap = pci_pcie_cap(dev);
        if (!cap)
                return -EINVAL;
 
@@ -2515,7 +2551,7 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
 
        v = (ffs(rq) - 8) << 12;
 
-       cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
+       cap = pci_pcie_cap(dev);
        if (!cap)
                goto out;
 
@@ -2575,7 +2611,7 @@ int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
                        return reg;
        }
 
-       dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
+       dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
        return 0;
 }
 
@@ -2625,7 +2661,7 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
 
 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
-spinlock_t resource_alignment_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(resource_alignment_lock);
 
 /**
  * pci_specified_resource_alignment - get resource alignment specified by user.
@@ -2758,6 +2794,11 @@ int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
        return 1;
 }
 
+void __weak pci_fixup_cardbus(struct pci_bus *bus)
+{
+}
+EXPORT_SYMBOL(pci_fixup_cardbus);
+
 static int __init pci_setup(char *str)
 {
        while (str) {