/* Reset the chip. */
iowrite32(0x80000000, ioaddr + DMACtrl);
- ret = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
+ ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
if (ret)
return ret;
dev_kfree_skb_irq(skb);
yp->tx_skbuff[entry] = NULL;
}
- if (yp->tx_full
- && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
+ if (yp->tx_full &&
+ yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
/* The ring is no longer full, clear tbusy. */
yp->tx_full = 0;
netif_wake_queue(dev);
}
#endif
- if (yp->tx_full
- && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
+ if (yp->tx_full &&
+ yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
/* The ring is no longer full, clear tbusy. */
yp->tx_full = 0;
netif_wake_queue(dev);
return 0;
case SIOCSMIIREG: /* Write MII PHY register. */
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
if (data->phy_id == np->phys[0]) {
u16 value = data->val_in;
switch (data->reg_num) {