#include "rt2x00pci.h"
/*
- * Beacon handlers.
- */
-int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct rt2x00_intf *intf = vif_to_intf(control->vif);
- struct queue_entry_priv_pci_tx *priv_tx;
- struct skb_frame_desc *skbdesc;
-
- if (unlikely(!intf->beacon))
- return -ENOBUFS;
-
- priv_tx = intf->beacon->priv_data;
-
- /*
- * Fill in skb descriptor
- */
- skbdesc = get_skb_frame_desc(skb);
- memset(skbdesc, 0, sizeof(*skbdesc));
- skbdesc->data = skb->data;
- skbdesc->data_len = skb->len;
- skbdesc->desc = priv_tx->desc;
- skbdesc->desc_len = intf->beacon->queue->desc_size;
- skbdesc->entry = intf->beacon;
-
- /*
- * Just in case mac80211 doesn't set this correctly,
- * but we need this queue set for the descriptor
- * initialization.
- */
- control->queue = IEEE80211_TX_QUEUE_BEACON;
- rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
-
- /*
- * Enable beacon generation.
- * Write entire beacon with descriptor to register,
- * and kick the beacon generator.
- */
- memcpy(priv_tx->data, skb->data, skb->len);
- rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);
-
-/*
* TX data handlers.
*/
-int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
- struct data_queue *queue, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
+int rt2x00pci_write_tx_data(struct queue_entry *entry)
{
- struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
- struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
+ struct queue_entry_priv_pci *entry_priv = entry->priv_data;
struct skb_frame_desc *skbdesc;
u32 word;
- if (rt2x00queue_full(queue))
- return -EINVAL;
-
- rt2x00_desc_read(priv_tx->desc, 0, &word);
+ rt2x00_desc_read(entry_priv->desc, 0, &word);
- if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
- rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
- ERROR(rt2x00dev,
- "Arrived at non-free entry in the non-full queue %d.\n"
+ /*
+ * This should not happen, we already checked the entry
+ * was ours. When the hardware disagrees there has been
+ * a queue corruption!
+ */
+ if (unlikely(rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
+ rt2x00_get_field32(word, TXD_ENTRY_VALID))) {
+ ERROR(entry->queue->rt2x00dev,
+ "Corrupt queue %d, accessing entry which is not ours.\n"
"Please file bug report to %s.\n",
- control->queue, DRV_PROJECT);
+ entry->queue->qid, DRV_PROJECT);
return -EINVAL;
}
/*
* Fill in skb descriptor
*/
- skbdesc = get_skb_frame_desc(skb);
- memset(skbdesc, 0, sizeof(*skbdesc));
- skbdesc->data = skb->data;
- skbdesc->data_len = queue->data_size;
- skbdesc->desc = priv_tx->desc;
- skbdesc->desc_len = queue->desc_size;
- skbdesc->entry = entry;
-
- memcpy(priv_tx->data, skb->data, skb->len);
- rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
-
- rt2x00queue_index_inc(queue, Q_INDEX);
+ skbdesc = get_skb_frame_desc(entry->skb);
+ skbdesc->desc = entry_priv->desc;
+ skbdesc->desc_len = entry->queue->desc_size;
return 0;
}
{
struct data_queue *queue = rt2x00dev->rx;
struct queue_entry *entry;
- struct queue_entry_priv_pci_rx *priv_rx;
- struct ieee80211_hdr *hdr;
+ struct queue_entry_priv_pci *entry_priv;
struct skb_frame_desc *skbdesc;
- struct rxdone_entry_desc rxdesc;
- int header_size;
- int align;
u32 word;
while (1) {
entry = rt2x00queue_get_entry(queue, Q_INDEX);
- priv_rx = entry->priv_data;
- rt2x00_desc_read(priv_rx->desc, 0, &word);
+ entry_priv = entry->priv_data;
+ rt2x00_desc_read(entry_priv->desc, 0, &word);
if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
break;
- memset(&rxdesc, 0, sizeof(rxdesc));
- rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
-
- hdr = (struct ieee80211_hdr *)priv_rx->data;
- header_size =
- ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
-
/*
- * The data behind the ieee80211 header must be
- * aligned on a 4 byte boundary.
- */
- align = header_size % 4;
-
- /*
- * Allocate the sk_buffer, initialize it and copy
- * all data into it.
- */
- entry->skb = dev_alloc_skb(rxdesc.size + align);
- if (!entry->skb)
- return;
-
- skb_reserve(entry->skb, align);
- memcpy(skb_put(entry->skb, rxdesc.size),
- priv_rx->data, rxdesc.size);
-
- /*
- * Fill in skb descriptor
+ * Fill in desc fields of the skb descriptor
*/
skbdesc = get_skb_frame_desc(entry->skb);
- memset(skbdesc, 0, sizeof(*skbdesc));
- skbdesc->data = entry->skb->data;
- skbdesc->data_len = queue->data_size;
- skbdesc->desc = priv_rx->desc;
- skbdesc->desc_len = queue->desc_size;
- skbdesc->entry = entry;
+ skbdesc->desc = entry_priv->desc;
+ skbdesc->desc_len = entry->queue->desc_size;
/*
* Send the frame to rt2x00lib for further processing.
*/
- rt2x00lib_rxdone(entry, &rxdesc);
-
- if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
- rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
- rt2x00_desc_write(priv_rx->desc, 0, word);
- }
-
- rt2x00queue_index_inc(queue, Q_INDEX);
+ rt2x00lib_rxdone(rt2x00dev, entry);
}
}
EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
-void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
- struct txdone_entry_desc *txdesc)
-{
- struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
- u32 word;
-
- txdesc->control = &priv_tx->control;
- rt2x00lib_txdone(entry, txdesc);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
-
- rt2x00_desc_read(priv_tx->desc, 0, &word);
- rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
- rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
- rt2x00_desc_write(priv_tx->desc, 0, word);
-
- rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
-
- /*
- * If the data queue was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- if (!rt2x00queue_full(entry->queue))
- ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
-
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
-
/*
* Device initialization handlers.
*/
-#define dma_size(__queue) \
-({ \
- (__queue)->limit * \
- ((__queue)->desc_size + (__queue)->data_size);\
-})
-
-#define priv_offset(__queue, __base, __i) \
-({ \
- (__base) + ((__i) * (__queue)->desc_size); \
-})
-
-#define data_addr_offset(__queue, __base, __i) \
-({ \
- (__base) + \
- ((__queue)->limit * (__queue)->desc_size) + \
- ((__i) * (__queue)->data_size); \
-})
-
-#define data_dma_offset(__queue, __base, __i) \
-({ \
- (__base) + \
- ((__queue)->limit * (__queue)->desc_size) + \
- ((__i) * (__queue)->data_size); \
-})
-
static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
struct data_queue *queue)
{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
- struct queue_entry_priv_pci_tx *priv_tx;
- void *data_addr;
- dma_addr_t data_dma;
+ struct queue_entry_priv_pci *entry_priv;
+ void *addr;
+ dma_addr_t dma;
unsigned int i;
/*
* Allocate DMA memory for descriptor and buffer.
*/
- data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma);
- if (!data_addr)
+ addr = dma_alloc_coherent(rt2x00dev->dev,
+ queue->limit * queue->desc_size,
+ &dma, GFP_KERNEL | GFP_DMA);
+ if (!addr)
return -ENOMEM;
+ memset(addr, 0, queue->limit * queue->desc_size);
+
/*
* Initialize all queue entries to contain valid addresses.
*/
for (i = 0; i < queue->limit; i++) {
- priv_tx = queue->entries[i].priv_data;
- priv_tx->desc = priv_offset(queue, data_addr, i);
- priv_tx->data = data_addr_offset(queue, data_addr, i);
- priv_tx->dma = data_dma_offset(queue, data_dma, i);
+ entry_priv = queue->entries[i].priv_data;
+ entry_priv->desc = addr + i * queue->desc_size;
+ entry_priv->desc_dma = dma + i * queue->desc_size;
}
return 0;
static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
struct data_queue *queue)
{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
- struct queue_entry_priv_pci_tx *priv_tx = queue->entries[0].priv_data;
-
- if (priv_tx->data)
- pci_free_consistent(pci_dev, dma_size(queue),
- priv_tx->data, priv_tx->dma);
- priv_tx->data = NULL;
+ struct queue_entry_priv_pci *entry_priv =
+ queue->entries[0].priv_data;
+
+ if (entry_priv->desc)
+ dma_free_coherent(rt2x00dev->dev,
+ queue->limit * queue->desc_size,
+ entry_priv->desc, entry_priv->desc_dma);
+ entry_priv->desc = NULL;
}
int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
+ struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
struct data_queue *queue;
int status;
if (status) {
ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
pci_dev->irq, status);
- return status;
+ goto exit;
}
return 0;
exit:
- rt2x00pci_uninitialize(rt2x00dev);
+ queue_for_each(rt2x00dev, queue)
+ rt2x00pci_free_queue_dma(rt2x00dev, queue);
return status;
}
/*
* Free irq line.
*/
- free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
+ free_irq(to_pci_dev(rt2x00dev->dev)->irq, rt2x00dev);
/*
* Free DMA
kfree(rt2x00dev->eeprom);
rt2x00dev->eeprom = NULL;
- if (rt2x00dev->csr_addr) {
- iounmap(rt2x00dev->csr_addr);
- rt2x00dev->csr_addr = NULL;
+ if (rt2x00dev->csr.base) {
+ iounmap(rt2x00dev->csr.base);
+ rt2x00dev->csr.base = NULL;
}
}
static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
+ struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
- rt2x00dev->csr_addr = ioremap(pci_resource_start(pci_dev, 0),
+ rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
pci_resource_len(pci_dev, 0));
- if (!rt2x00dev->csr_addr)
+ if (!rt2x00dev->csr.base)
goto exit;
rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
if (pci_set_mwi(pci_dev))
ERROR_PROBE("MWI not available.\n");
- if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
- pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
+ if (dma_set_mask(&pci_dev->dev, DMA_32BIT_MASK)) {
ERROR_PROBE("PCI DMA not supported.\n");
retval = -EIO;
goto exit_disable_device;
pci_set_drvdata(pci_dev, hw);
rt2x00dev = hw->priv;
- rt2x00dev->dev = pci_dev;
+ rt2x00dev->dev = &pci_dev->dev;
rt2x00dev->ops = ops;
rt2x00dev->hw = hw;