#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
+#include <linux/slab.h>
#include <mach/npe.h>
#include <mach/qmgr.h>
-#define DEBUG_QUEUES 0
#define DEBUG_DESC 0
#define DEBUG_RX 0
#define DEBUG_TX 0
#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
+/*
+ * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
+ * A (10 bits), B (10 bits) and C (12 bits).
+ * IXP42x HSS clock generator operation (verified with an oscilloscope):
+ * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
+ * The clock sequence consists of (C - B) states of 0s and 1s, each state is
+ * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
+ * (A + 1) bits wide.
+ *
+ * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
+ * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
+ * minumum freq = 66.666 MHz / (A + 1)
+ * maximum freq = 66.666 MHz / A
+ *
+ * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
+ * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
+ * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
+ * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
+ * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
+ * The sequence consists of 4 complete clock periods, thus the average
+ * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
+ * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
+ */
/* hss_config, LUT entries */
#define TDMMAP_UNASSIGNED 0
unsigned int clock_type, clock_rate, loopback;
unsigned int initialized, carrier;
u8 hdlc_cfg;
+ u32 clock_reg;
};
/* NPE message structure */
msg.cmd = PORT_CONFIG_WRITE;
msg.hss_port = port->id;
msg.index = HSS_CONFIG_CLOCK_CR;
- msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
+ msg.data32 = port->clock_reg;
hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
memset(&msg, 0, sizeof(msg));
#endif
}
-static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
-{
-#if DEBUG_QUEUES
- static struct {
- int queue;
- char *name;
- } names[] = {
- { HSS0_PKT_TX0_QUEUE, "TX#0 " },
- { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
- { HSS0_PKT_RX_QUEUE, "RX#0 " },
- { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
- { HSS1_PKT_TX0_QUEUE, "TX#1 " },
- { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
- { HSS1_PKT_RX_QUEUE, "RX#1 " },
- { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
- };
- int i;
-
- for (i = 0; i < ARRAY_SIZE(names); i++)
- if (names[i].queue == queue)
- break;
-
- printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
- i < ARRAY_SIZE(names) ? names[i].name : "",
- is_get ? "->" : "<-", phys);
-#endif
-}
-
-static inline u32 queue_get_entry(unsigned int queue)
-{
- u32 phys = qmgr_get_entry(queue);
- debug_queue(queue, 1, phys);
- return phys;
-}
-
static inline int queue_get_desc(unsigned int queue, struct port *port,
int is_tx)
{
u32 phys, tab_phys, n_desc;
struct desc *tab;
- if (!(phys = queue_get_entry(queue)))
+ if (!(phys = qmgr_get_entry(queue)))
return -1;
BUG_ON(phys & 0x1F);
static inline void queue_put_desc(unsigned int queue, u32 phys,
struct desc *desc)
{
- debug_queue(queue, 0, phys);
debug_desc(phys, desc);
BUG_ON(phys & 0x1F);
qmgr_put_entry(queue, phys);
- BUG_ON(qmgr_stat_overflow(queue));
+ /* Don't check for queue overflow here, we've allocated sufficient
+ length and queues >= 32 don't support this check anyway. */
}
printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
#endif
qmgr_disable_irq(queue_ids[port->id].rx);
- netif_rx_schedule(dev, &port->napi);
+ napi_schedule(&port->napi);
}
static int hss_hdlc_poll(struct napi_struct *napi, int budget)
if ((n = queue_get_desc(rxq, port, 0)) < 0) {
#if DEBUG_RX
printk(KERN_DEBUG "%s: hss_hdlc_poll"
- " netif_rx_complete\n", dev->name);
+ " napi_complete\n", dev->name);
#endif
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
qmgr_enable_irq(rxq);
if (!qmgr_stat_empty(rxq) &&
- netif_rx_reschedule(dev, napi)) {
+ napi_reschedule(napi)) {
#if DEBUG_RX
printk(KERN_DEBUG "%s: hss_hdlc_poll"
- " netif_rx_reschedule succeeded\n",
+ " napi_reschedule succeeded\n",
dev->name);
#endif
qmgr_disable_irq(rxq);
dma_unmap_single(&dev->dev, desc->data,
RX_SIZE, DMA_FROM_DEVICE);
#else
- dma_sync_single(&dev->dev, desc->data,
- RX_SIZE, DMA_FROM_DEVICE);
+ dma_sync_single_for_cpu(&dev->dev, desc->data,
+ RX_SIZE, DMA_FROM_DEVICE);
memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
ALIGN(desc->pkt_len, 4) / 4);
#endif
free_buffer_irq(port->tx_buff_tab[n_desc]);
port->tx_buff_tab[n_desc] = NULL;
- start = qmgr_stat_empty(port->plat->txreadyq);
+ start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
queue_put_desc(port->plat->txreadyq,
tx_desc_phys(port, n_desc), desc);
- if (start) {
+ if (start) { /* TX-ready queue was empty */
#if DEBUG_TX
printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
" ready\n", dev->name);
queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
dev->trans_start = jiffies;
- if (qmgr_stat_empty(txreadyq)) {
+ if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
#if DEBUG_TX
printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
#endif
netif_stop_queue(dev);
/* we could miss TX ready interrupt */
- if (!qmgr_stat_empty(txreadyq)) {
+ if (!qmgr_stat_below_low_watermark(txreadyq)) {
#if DEBUG_TX
printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
dev->name);
{
int err;
- err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
+ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
+ "%s:RX-free", port->netdev->name);
if (err)
return err;
- err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
+ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
+ "%s:RX", port->netdev->name);
if (err)
goto rel_rxfree;
- err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
+ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
+ "%s:TX", port->netdev->name);
if (err)
goto rel_rx;
- err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
+ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
+ "%s:TX-ready", port->netdev->name);
if (err)
goto rel_tx;
- err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
+ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
+ "%s:TX-done", port->netdev->name);
if (err)
goto rel_txready;
return 0;
hss_start_hdlc(port);
/* we may already have RX data, enables IRQ */
- netif_rx_schedule(dev, &port->napi);
+ napi_schedule(&port->napi);
return 0;
err_unlock:
}
}
+static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
+ u32 *best, u32 *best_diff, u32 *reg)
+{
+ /* a is 10-bit, b is 10-bit, c is 12-bit */
+ u64 new_rate;
+ u32 new_diff;
+
+ new_rate = ixp4xx_timer_freq * (u64)(c + 1);
+ do_div(new_rate, a * (c + 1) + b + 1);
+ new_diff = abs((u32)new_rate - rate);
+
+ if (new_diff < *best_diff) {
+ *best = new_rate;
+ *best_diff = new_diff;
+ *reg = (a << 22) | (b << 12) | c;
+ }
+ return new_diff;
+}
+
+static void find_best_clock(u32 rate, u32 *best, u32 *reg)
+{
+ u32 a, b, diff = 0xFFFFFFFF;
+
+ a = ixp4xx_timer_freq / rate;
+
+ if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
+ check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
+ return;
+ }
+ if (a == 0) { /* > 66.666 MHz */
+ a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
+ rate = ixp4xx_timer_freq;
+ }
+
+ if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
+ check_clock(rate, a - 1, 1, 1, best, &diff, reg);
+ return;
+ }
+
+ for (b = 0; b < 0x400; b++) {
+ u64 c = (b + 1) * (u64)rate;
+ do_div(c, ixp4xx_timer_freq - rate * a);
+ c--;
+ if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
+ if (b == 0 && /* also try a bit higher rate */
+ !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
+ return;
+ check_clock(rate, a, b, 0xFFF, best, &diff, reg);
+ return;
+ }
+ if (!check_clock(rate, a, b, c, best, &diff, reg))
+ return;
+ if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
+ return;
+ }
+}
static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
}
memset(&new_line, 0, sizeof(new_line));
new_line.clock_type = port->clock_type;
- new_line.clock_rate = 2048000; /* FIXME */
+ new_line.clock_rate = port->clock_rate;
new_line.loopback = port->loopback;
if (copy_to_user(line, &new_line, size))
return -EFAULT;
return -EINVAL;
port->clock_type = clk; /* Update settings */
- /* FIXME port->clock_rate = new_line.clock_rate */;
+ if (clk == CLOCK_INT)
+ find_best_clock(new_line.clock_rate, &port->clock_rate,
+ &port->clock_reg);
+ else {
+ port->clock_rate = 0;
+ port->clock_reg = CLK42X_SPEED_2048KHZ;
+ }
port->loopback = new_line.loopback;
spin_lock_irqsave(&npe_lock, flags);
* initialization
****************************************************************************/
+static const struct net_device_ops hss_hdlc_ops = {
+ .ndo_open = hss_hdlc_open,
+ .ndo_stop = hss_hdlc_close,
+ .ndo_change_mtu = hdlc_change_mtu,
+ .ndo_start_xmit = hdlc_start_xmit,
+ .ndo_do_ioctl = hss_hdlc_ioctl,
+};
+
static int __devinit hss_init_one(struct platform_device *pdev)
{
struct port *port;
return -ENOMEM;
if ((port->npe = npe_request(0)) == NULL) {
- err = -ENOSYS;
+ err = -ENODEV;
goto err_free;
}
hdlc = dev_to_hdlc(dev);
hdlc->attach = hss_hdlc_attach;
hdlc->xmit = hss_hdlc_xmit;
- dev->open = hss_hdlc_open;
- dev->stop = hss_hdlc_close;
- dev->do_ioctl = hss_hdlc_ioctl;
+ dev->netdev_ops = &hss_hdlc_ops;
dev->tx_queue_len = 100;
port->clock_type = CLOCK_EXT;
- port->clock_rate = 2048000;
+ port->clock_rate = 0;
+ port->clock_reg = CLK42X_SPEED_2048KHZ;
port->id = pdev->id;
port->dev = &pdev->dev;
port->plat = pdev->dev.platform_data;
if ((ixp4xx_read_feature_bits() &
(IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
(IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
- return -ENOSYS;
+ return -ENODEV;
spin_lock_init(&npe_lock);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff