ath9k_hw: move the cck channel 14 INI to the AR9002 hw code

[safe/jmp/linux-2.6] / drivers / net / vxge / vxge-config.c

diff --git a/drivers/net/vxge/vxge-config.c b/drivers/net/vxge/vxge-config.c
index 933237e..32a75fa 100644 (file)
--- a/drivers/net/vxge/vxge-config.c
+++ b/drivers/net/vxge/vxge-config.c
@@ -2157,6 +2157,28 @@ exit:
 }
 
 /*
+ * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
+ */
+enum vxge_hw_status
+vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
+{
+       struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
+       enum vxge_hw_status status = VXGE_HW_OK;
+       int i = 0, j = 0;
+
+       for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
+               if (!((vpath_mask) & vxge_mBIT(i)))
+                       continue;
+               vpmgmt_reg = hldev->vpmgmt_reg[i];
+               for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
+                       if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
+                       & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
+                               return VXGE_HW_FAIL;
+               }
+       }
+       return status;
+}
+/*
  * vxge_hw_mgmt_reg_Write - Write Titan register.
  */
 enum vxge_hw_status
@@ -3860,6 +3882,30 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
        return status;
 }
 
+void
+vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
+{
+       struct __vxge_hw_virtualpath *vpath;
+       struct vxge_hw_vpath_reg __iomem *vp_reg;
+       struct vxge_hw_vp_config *config;
+       u64 val64;
+
+       vpath = &hldev->virtual_paths[vp_id];
+       vp_reg = vpath->vp_reg;
+       config = vpath->vp_config;
+
+       if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
+               val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
+
+               if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
+                       config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
+                       val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
+                       writeq(val64,
+                       &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
+               }
+       }
+       return;
+}
 /*
  * __vxge_hw_vpath_initialize
  * This routine is the final phase of init which initializes the