tg3: Add version reporting for hardware selfboot

[safe/jmp/linux-2.6] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 814d82b..cb4c62a 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -44,26 +44,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57760     0x1690
 #define  TG3PCI_DEVICE_TIGON3_57790     0x1694
 #define  TG3PCI_DEVICE_TIGON3_57720     0x168c
-#define TG3PCI_COMMAND                 0x00000004
-#define TG3PCI_STATUS                  0x00000006
-#define TG3PCI_CCREVID                 0x00000008
-#define TG3PCI_CACHELINESZ             0x0000000c
-#define TG3PCI_LATTIMER                        0x0000000d
-#define TG3PCI_HEADERTYPE              0x0000000e
-#define TG3PCI_BIST                    0x0000000f
-#define TG3PCI_BASE0_LOW               0x00000010
-#define TG3PCI_BASE0_HIGH              0x00000014
-/* 0x18 --> 0x2c unused */
-#define TG3PCI_SUBSYSVENID             0x0000002c
-#define TG3PCI_SUBSYSID                        0x0000002e
-#define TG3PCI_ROMADDR                 0x00000030
-#define TG3PCI_CAPLIST                 0x00000034
-/* 0x35 --> 0x3c unused */
-#define TG3PCI_IRQ_LINE                        0x0000003c
-#define TG3PCI_IRQ_PIN                 0x0000003d
-#define TG3PCI_MIN_GNT                 0x0000003e
-#define TG3PCI_MAX_LAT                 0x0000003f
-/* 0x40 --> 0x64 unused */
+/* 0x04 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL          0x00000068
@@ -114,10 +95,6 @@
 #define  CHIPREV_ID_5752_A1             0x6001
 #define  CHIPREV_ID_5714_A2             0x9002
 #define  CHIPREV_ID_5906_A1             0xc001
-#define  CHIPREV_ID_5784_A0             0x5784000
-#define  CHIPREV_ID_5784_A1             0x5784001
-#define  CHIPREV_ID_5761_A0             0x5761000
-#define  CHIPREV_ID_5761_A1             0x5761001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -1742,6 +1719,12 @@
 
 #define TG3_OTP_DEFAULT                        0x286c1640
 
+/* Hardware Selfboot NVRAM layout */
+#define TG3_NVM_HWSB_CFG1              0x00000004
+#define  TG3_NVM_HWSB_CFG1_MAJMSK      0xf8000000
+#define  TG3_NVM_HWSB_CFG1_MAJSFT      27
+#define  TG3_NVM_HWSB_CFG1_MINMSK      0x07c00000
+#define  TG3_NVM_HWSB_CFG1_MINSFT      22
 
 #define TG3_EEPROM_MAGIC               0x669955aa
 #define TG3_EEPROM_MAGIC_FW            0xa5000000
@@ -1760,6 +1743,10 @@
 #define TG3_NVM_DIRENT_SIZE            0xc
 #define TG3_NVM_DIRTYPE_SHIFT          24
 #define TG3_NVM_DIRTYPE_ASFINI         1
+#define TG3_NVM_PTREV_BCVER            0x94
+#define TG3_NVM_BCVER_MAJMSK           0x0000ff00
+#define TG3_NVM_BCVER_MAJSFT           8
+#define TG3_NVM_BCVER_MINMSK           0x000000ff
 
 #define TG3_EEPROM_SB_F1R0_EDH_OFF     0x10
 #define TG3_EEPROM_SB_F1R2_EDH_OFF     0x14
@@ -1946,12 +1933,6 @@
 #define MII_TG3_ISTAT                  0x1a /* IRQ status register */
 #define MII_TG3_IMASK                  0x1b /* IRQ mask register */
 
-#define MII_TG3_MISC_SHDW              0x1c
-#define MII_TG3_MISC_SHDW_WREN         0x8000
-#define MII_TG3_MISC_SHDW_APD_SEL      0x2800
-
-#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
-
 /* ISTAT/IMASK event bits */
 #define MII_TG3_INT_LINKCHG            0x0002
 #define MII_TG3_INT_SPEEDCHG           0x0004
@@ -1960,7 +1941,9 @@
 
 #define MII_TG3_MISC_SHDW              0x1c
 #define MII_TG3_MISC_SHDW_WREN         0x8000
-#define MII_TG3_MISC_SHDW_SCR5_SEL     0x1400
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
+#define MII_TG3_MISC_SHDW_APD_ENABLE   0x0020
 #define MII_TG3_MISC_SHDW_APD_SEL      0x2800
 
 #define MII_TG3_MISC_SHDW_SCR5_C125OE  0x0001
@@ -1968,9 +1951,8 @@
 #define MII_TG3_MISC_SHDW_SCR5_SDTL    0x0004
 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM  0x0008
 #define MII_TG3_MISC_SHDW_SCR5_LPED    0x0010
+#define MII_TG3_MISC_SHDW_SCR5_SEL     0x1400
 
-#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
-#define MII_TG3_MISC_SHDW_APD_ENABLE   0x0020
 
 #define MII_TG3_EPHY_TEST              0x1f /* 5906 PHY register */
 #define MII_TG3_EPHY_SHADOW_EN         0x80
@@ -1995,6 +1977,14 @@
 /* APE shared memory.  Accessible through BAR1 */
 #define TG3_APE_FW_STATUS              0x400c
 #define  APE_FW_STATUS_READY            0x00000100
+#define TG3_APE_FW_VERSION             0x4018
+#define  APE_FW_VERSION_MAJMSK          0xff000000
+#define  APE_FW_VERSION_MAJSFT          24
+#define  APE_FW_VERSION_MINMSK          0x00ff0000
+#define  APE_FW_VERSION_MINSFT          16
+#define  APE_FW_VERSION_REVMSK          0x0000ff00
+#define  APE_FW_VERSION_REVSFT          8
+#define  APE_FW_VERSION_BLDMSK          0x000000ff
 #define TG3_APE_HOST_SEG_SIG           0x4200
 #define  APE_HOST_SEG_SIG_MAGIC                 0x484f5354
 #define TG3_APE_HOST_SEG_LEN           0x4204
@@ -2790,6 +2780,11 @@ struct tg3 {
 #define SST_25VF0X0_PAGE_SIZE          4098
 
        struct ethtool_coalesce         coal;
+
+       /* firmware info */
+       const char                      *fw_needed;
+       const struct firmware           *fw;
+       u32                             fw_len; /* includes BSS */
 };
 
 #endif /* !(_T3_H) */