#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
+#define SG_DIG_IS_SERDES 0x00000100
#define SG_DIG_COMMA_DETECTOR 0x00000008
#define SG_DIG_MAC_ACK_STATUS 0x00000004
#define SG_DIG_AUTONEG_COMPLETE 0x00000002
#define TG3_CPMU_HST_ACC 0x0000361c
#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
-/* 0x3620 --> 0x3630 unused */
+/* 0x3620 --> 0x362c unused */
+#define TG3_CPMU_STATUS 0x0000362c
+#define TG3_CPMU_STATUS_PCIE_FUNC 0x20000000
#define TG3_CPMU_CLCK_STAT 0x00003630
#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
+#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
+#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
+#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
+#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
+#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
+#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
+#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
+#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
+#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
+#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
+#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
+#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
+#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
+#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
+#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
+#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
+#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
+#define FLASH_5717VENDOR_ST_25USPT 0x03400002
+#define FLASH_5717VENDOR_ST_45USPT 0x03400001
#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
#define FLASH_5752PAGE_SIZE_256 0x00000000
#define FLASH_5752PAGE_SIZE_512 0x10000000
struct tx_ring_info {
struct sk_buff *skb;
- u32 prev_vlan_tag;
};
struct tg3_config_info {
#define TG3_FLG3_5701_DMA_BUG 0x00000008
#define TG3_FLG3_USE_PHYLIB 0x00000010
#define TG3_FLG3_MDIOBUS_INITED 0x00000020
-#define TG3_FLG3_MDIOBUS_PAUSED 0x00000040
#define TG3_FLG3_PHY_CONNECTED 0x00000080
#define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
struct mii_bus *mdio_bus;
int mdio_irq[PHY_MAX_ADDR];
+ u8 phy_addr;
+
/* PHY info */
u32 phy_id;
#define PHY_ID_MASK 0xfffffff0