#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.101"
-#define DRV_MODULE_RELDATE "August 28, 2009"
+#define DRV_MODULE_VERSION "3.102"
+#define DRV_MODULE_RELDATE "September 1, 2009"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
* replace things like '% foo' with '& (foo - 1)'.
*/
#define TG3_RX_RCB_RING_SIZE(tp) \
- ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
+ (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
+ !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
#define TG3_TX_RING_SIZE 512
#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
static void tg3_switch_clocks(struct tg3 *tp)
{
- u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
+ u32 clock_ctrl;
u32 orig_clock_ctrl;
if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
return;
+ clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
+
orig_clock_ctrl = clock_ctrl;
clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
CLOCK_CTRL_CLKRUN_OENABLE |
*val = 0x0;
- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
+ frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK);
udelay(80);
}
- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
+ frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK);
struct tg3 *tp = bp->priv;
u32 val;
- if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
- return -EAGAIN;
+ spin_lock_bh(&tp->lock);
if (tg3_readphy(tp, reg, &val))
- return -EIO;
+ val = -EIO;
+
+ spin_unlock_bh(&tp->lock);
return val;
}
static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
{
struct tg3 *tp = bp->priv;
+ u32 ret = 0;
- if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
- return -EAGAIN;
+ spin_lock_bh(&tp->lock);
if (tg3_writephy(tp, reg, val))
- return -EIO;
+ ret = -EIO;
- return 0;
+ spin_unlock_bh(&tp->lock);
+
+ return ret;
}
static int tg3_mdio_reset(struct mii_bus *bp)
static void tg3_mdio_start(struct tg3 *tp)
{
- if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
- mutex_lock(&tp->mdio_bus->mdio_lock);
- tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
- mutex_unlock(&tp->mdio_bus->mdio_lock);
- }
-
tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
tw32_f(MAC_MI_MODE, tp->mi_mode);
udelay(80);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+ u32 funcnum, is_serdes;
+
+ funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
+ if (funcnum)
+ tp->phy_addr = 2;
+ else
+ tp->phy_addr = 1;
+
+ is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
+ if (is_serdes)
+ tp->phy_addr += 7;
+ } else
+ tp->phy_addr = PHY_ADDR;
+
if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
tg3_mdio_config_5785(tp);
}
-static void tg3_mdio_stop(struct tg3 *tp)
-{
- if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
- mutex_lock(&tp->mdio_bus->mdio_lock);
- tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
- mutex_unlock(&tp->mdio_bus->mdio_lock);
- }
-}
-
static int tg3_mdio_init(struct tg3 *tp)
{
int i;
tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
mdiobus_unregister(tp->mdio_bus);
mdiobus_free(tp->mdio_bus);
- tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
}
}
struct tg3 *tp = netdev_priv(dev);
struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
- spin_lock(&tp->lock);
+ spin_lock_bh(&tp->lock);
mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
MAC_MODE_HALF_DUPLEX);
tp->link_config.active_speed = phydev->speed;
tp->link_config.active_duplex = phydev->duplex;
- spin_unlock(&tp->lock);
+ spin_unlock_bh(&tp->lock);
if (linkmesg)
tg3_link_report(tp);
if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
return;
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
struct net_device *dev_peer;
dev_peer = pci_get_drvdata(tp->pdev_peer);
mss = 0;
if ((mss = skb_shinfo(skb)->gso_size) != 0) {
int tcp_opt_len, ip_tcp_len;
+ u32 hdrlen;
if (skb_header_cloned(skb) &&
pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
}
if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
- mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
+ hdrlen = skb_headlen(skb) - ETH_HLEN;
else {
struct iphdr *iph = ip_hdr(skb);
iph->check = 0;
iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
- mss |= (ip_tcp_len + tcp_opt_len) << 9;
+ hdrlen = ip_tcp_len + tcp_opt_len;
}
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+ mss |= (hdrlen & 0xc) << 12;
+ if (hdrlen & 0x10)
+ base_flags |= 0x00000010;
+ base_flags |= (hdrlen & 0x3e0) << 5;
+ } else
+ mss |= hdrlen << 9;
+
base_flags |= (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
len = skb_headlen(skb);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
+ !mss && skb->len > ETH_DATA_LEN)
+ base_flags |= TXD_FLAG_JMB_PKT;
+
tg3_set_txd(tnapi, entry, mapping, len, base_flags,
(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
tg3_nvram_lock(tp);
- tg3_mdio_stop(tp);
-
tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
/* No matching tg3_nvram_unlock() after this because
tg3_mdio_start(tp);
if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
- tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
+ tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
val = tr32(0x7c00);
tw32(0x7c00, val | (1 << 25));
/* Disable all receive return rings but the first. */
- if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+ limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
+ else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
return err;
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
/* This value is determined during the probe time DMA
* engine test, tg3_test_dma.
*/
BDINFO_FLAGS_DISABLED);
}
- val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+ val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
+ (RX_STD_MAX_SIZE << 2);
+ else
+ val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
} else
val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
tpr->rx_jmb_ptr);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+ tw32(STD_REPLENISH_LWM, 32);
+ tw32(JMB_REPLENISH_LWM, 16);
+ }
+
tg3_rings_reset(tp);
/* Initialize MAC address and backoff seed. */
struct tg3_napi *tnapi = &tp->napi[0];
struct net_device *dev = tp->dev;
int err, i, intr_ok = 0;
+ u32 val;
if (!netif_running(dev))
return -ENODEV;
free_irq(tnapi->irq_vec, tnapi);
+ /*
+ * Turn off MSI one shot mode. Otherwise this test has no
+ * observable way to know whether the interrupt was delivered.
+ */
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
+ (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
+ val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
+ tw32(MSGINT_MODE, val);
+ }
+
err = request_irq(tnapi->irq_vec, tg3_test_isr,
IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
if (err)
if (err)
return err;
- if (intr_ok)
+ if (intr_ok) {
+ /* Reenable MSI one shot mode. */
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
+ (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
+ val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
+ tw32(MSGINT_MODE, val);
+ }
return 0;
+ }
return -EIO;
}
goto err_out2;
}
- if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
- if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
- u32 val = tr32(PCIE_TRANSACTION_CFG);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
+ (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
+ (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
+ u32 val = tr32(PCIE_TRANSACTION_CFG);
- tw32(PCIE_TRANSACTION_CFG,
- val | PCIE_TRANS_CFG_1SHOT_MSI);
- }
+ tw32(PCIE_TRANSACTION_CFG,
+ val | PCIE_TRANS_CFG_1SHOT_MSI);
}
}
del_timer_sync(&tp->timer);
+ tg3_phy_stop(tp);
+
tg3_full_lock(tp, 1);
#if 0
tg3_dump_state(tp);
cmd->speed = tp->link_config.active_speed;
cmd->duplex = tp->link_config.active_duplex;
}
- cmd->phy_address = PHY_ADDR;
+ cmd->phy_address = tp->phy_addr;
cmd->transceiver = XCVR_INTERNAL;
cmd->autoneg = tp->link_config.autoneg;
cmd->maxtxpkt = 0;
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
dev->features |= NETIF_F_TSO_ECN;
} else
dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
switch(cmd) {
case SIOCGMIIPHY:
- data->phy_id = PHY_ADDR;
+ data->phy_id = tp->phy_addr;
/* fallthru */
case SIOCGMIIREG: {
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
break; /* We have no PHY */
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
-
if (tp->link_config.phy_is_low_power)
return -EAGAIN;
}
}
+static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
+{
+ switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
+ case FLASH_5752PAGE_SIZE_256:
+ tp->nvram_pagesize = 256;
+ break;
+ case FLASH_5752PAGE_SIZE_512:
+ tp->nvram_pagesize = 512;
+ break;
+ case FLASH_5752PAGE_SIZE_1K:
+ tp->nvram_pagesize = 1024;
+ break;
+ case FLASH_5752PAGE_SIZE_2K:
+ tp->nvram_pagesize = 2048;
+ break;
+ case FLASH_5752PAGE_SIZE_4K:
+ tp->nvram_pagesize = 4096;
+ break;
+ case FLASH_5752PAGE_SIZE_264:
+ tp->nvram_pagesize = 264;
+ break;
+ case FLASH_5752PAGE_SIZE_528:
+ tp->nvram_pagesize = 528;
+ break;
+ }
+}
+
static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
{
u32 nvcfg1;
}
if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
- switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
- case FLASH_5752PAGE_SIZE_256:
- tp->nvram_pagesize = 256;
- break;
- case FLASH_5752PAGE_SIZE_512:
- tp->nvram_pagesize = 512;
- break;
- case FLASH_5752PAGE_SIZE_1K:
- tp->nvram_pagesize = 1024;
- break;
- case FLASH_5752PAGE_SIZE_2K:
- tp->nvram_pagesize = 2048;
- break;
- case FLASH_5752PAGE_SIZE_4K:
- tp->nvram_pagesize = 4096;
- break;
- case FLASH_5752PAGE_SIZE_264:
- tp->nvram_pagesize = 264;
- break;
- }
+ tg3_nvram_get_pagesize(tp, nvcfg1);
} else {
/* For eeprom, set pagesize to maximum eeprom size */
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
return;
}
- switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
- case FLASH_5752PAGE_SIZE_256:
+ tg3_nvram_get_pagesize(tp, nvcfg1);
+ if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
- tp->nvram_pagesize = 256;
- break;
- case FLASH_5752PAGE_SIZE_512:
- tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
- tp->nvram_pagesize = 512;
- break;
- case FLASH_5752PAGE_SIZE_1K:
- tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
- tp->nvram_pagesize = 1024;
- break;
- case FLASH_5752PAGE_SIZE_2K:
- tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
- tp->nvram_pagesize = 2048;
- break;
- case FLASH_5752PAGE_SIZE_4K:
- tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
- tp->nvram_pagesize = 4096;
- break;
- case FLASH_5752PAGE_SIZE_264:
- tp->nvram_pagesize = 264;
+}
+
+
+static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
+{
+ u32 nvcfg1;
+
+ nvcfg1 = tr32(NVRAM_CFG1);
+
+ switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+ case FLASH_5717VENDOR_ATMEL_EEPROM:
+ case FLASH_5717VENDOR_MICRO_EEPROM:
+ tp->nvram_jedecnum = JEDEC_ATMEL;
+ tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+ tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+
+ nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+ tw32(NVRAM_CFG1, nvcfg1);
+ return;
+ case FLASH_5717VENDOR_ATMEL_MDB011D:
+ case FLASH_5717VENDOR_ATMEL_ADB011B:
+ case FLASH_5717VENDOR_ATMEL_ADB011D:
+ case FLASH_5717VENDOR_ATMEL_MDB021D:
+ case FLASH_5717VENDOR_ATMEL_ADB021B:
+ case FLASH_5717VENDOR_ATMEL_ADB021D:
+ case FLASH_5717VENDOR_ATMEL_45USPT:
+ tp->nvram_jedecnum = JEDEC_ATMEL;
+ tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+ tp->tg3_flags2 |= TG3_FLG2_FLASH;
+
+ switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+ case FLASH_5717VENDOR_ATMEL_MDB021D:
+ case FLASH_5717VENDOR_ATMEL_ADB021B:
+ case FLASH_5717VENDOR_ATMEL_ADB021D:
+ tp->nvram_size = TG3_NVRAM_SIZE_256KB;
+ break;
+ default:
+ tp->nvram_size = TG3_NVRAM_SIZE_128KB;
+ break;
+ }
break;
- case FLASH_5752PAGE_SIZE_528:
- tp->nvram_pagesize = 528;
+ case FLASH_5717VENDOR_ST_M_M25PE10:
+ case FLASH_5717VENDOR_ST_A_M25PE10:
+ case FLASH_5717VENDOR_ST_M_M45PE10:
+ case FLASH_5717VENDOR_ST_A_M45PE10:
+ case FLASH_5717VENDOR_ST_M_M25PE20:
+ case FLASH_5717VENDOR_ST_A_M25PE20:
+ case FLASH_5717VENDOR_ST_M_M45PE20:
+ case FLASH_5717VENDOR_ST_A_M45PE20:
+ case FLASH_5717VENDOR_ST_25USPT:
+ case FLASH_5717VENDOR_ST_45USPT:
+ tp->nvram_jedecnum = JEDEC_ST;
+ tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+ tp->tg3_flags2 |= TG3_FLG2_FLASH;
+
+ switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+ case FLASH_5717VENDOR_ST_M_M25PE20:
+ case FLASH_5717VENDOR_ST_A_M25PE20:
+ case FLASH_5717VENDOR_ST_M_M45PE20:
+ case FLASH_5717VENDOR_ST_A_M45PE20:
+ tp->nvram_size = TG3_NVRAM_SIZE_256KB;
+ break;
+ default:
+ tp->nvram_size = TG3_NVRAM_SIZE_128KB;
+ break;
+ }
break;
+ default:
+ tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
+ return;
}
+
+ tg3_nvram_get_pagesize(tp, nvcfg1);
+ if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
+ tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
}
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
tg3_get_5906_nvram_info(tp);
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
tg3_get_57780_nvram_info(tp);
+ else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+ tg3_get_5717_nvram_info(tp);
else
tg3_get_nvram_info(tp);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
u32 prod_id_asic_rev;
- pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
- &prod_id_asic_rev);
+ if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
+ tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
+ tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
+ tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
+ pci_read_config_dword(tp->pdev,
+ TG3PCI_GEN2_PRODID_ASICREV,
+ &prod_id_asic_rev);
+ else
+ pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
+ &prod_id_asic_rev);
+
tp->pci_chip_rev_id = prod_id_asic_rev;
}
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
tp->misc_host_ctrl);
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
tp->pdev_peer = tg3_find_peer(tp);
/* Intentionally exclude ASIC_REV_5906 */
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
tp->irq_max = 1;
+#ifdef TG3_NAPI
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+ tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
+ tp->irq_max = TG3_IRQ_MAX_VECS;
+ }
+#endif
+
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
- (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
+ (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
tp->write32 = tg3_write_flush_reg32;
}
-
if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
tp->write32_tx_mbox = tg3_write32_tx_mbox;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
else
tg3_nvram_unlock(tp);
- }
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+ } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+ if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
+ mac_offset = 0xcc;
+ } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
mac_offset = 0x10;
/* First try to get it from MAC address mailbox. */
static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
{
- if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
tp->bufmgr_config.mbuf_read_dma_low_water =
DEFAULT_MB_RDMA_LOW_WATER_5705;
tp->bufmgr_config.mbuf_mac_rx_low_water =
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
dev->features |= NETIF_F_TSO_ECN;
}
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff