* All Rights Reserved.
*/
-#ifdef TC35815_NAPI
-#define DRV_VERSION "1.37-NAPI"
-#else
-#define DRV_VERSION "1.37"
-#endif
+#define DRV_VERSION "1.39"
static const char *version = "tc35815.c:v" DRV_VERSION "\n";
#define MODNAME "tc35815"
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/in.h>
+#include <linux/if_vlan.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/byteorder.h>
-/* First, a few definitions that the brave might change. */
-
-#define GATHER_TXINT /* On-Demand Tx Interrupt */
-#define WORKAROUND_LOSTCAR
-#define WORKAROUND_100HALF_PROMISC
-/* #define TC35815_USE_PACKEDBUFFER */
-
enum tc35815_chiptype {
TC35815CF = 0,
TC35815_NWU,
{ "TOSHIBA TC35815/TX4939" },
};
-static const struct pci_device_id tc35815_pci_tbl[] = {
+static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
{0,}
};
-MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
+MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
/* see MODULE_PARM_DESC */
static struct tc35815_options {
* Bit assignments
*/
/* DMA_Ctl bit asign ------------------------------------------------------- */
-#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
-#define DMA_RxAlign_1 0x00400000
-#define DMA_RxAlign_2 0x00800000
-#define DMA_RxAlign_3 0x00c00000
-#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
-#define DMA_IntMask 0x00040000 /* 1:Interupt mask */
-#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
-#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
-#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
-#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
-#define DMA_TestMode 0x00002000 /* 1:Test Mode */
-#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
-#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
+#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
+#define DMA_RxAlign_1 0x00400000
+#define DMA_RxAlign_2 0x00800000
+#define DMA_RxAlign_3 0x00c00000
+#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
+#define DMA_IntMask 0x00040000 /* 1:Interupt mask */
+#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
+#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
+#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
+#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
+#define DMA_TestMode 0x00002000 /* 1:Test Mode */
+#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
+#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
/* RxFragSize bit asign ---------------------------------------------------- */
-#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
-#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
+#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
+#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
/* MAC_Ctl bit asign ------------------------------------------------------- */
-#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
-#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
-#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
-#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
-#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
-#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
-#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
-#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
-#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
-#define MAC_Reset 0x00000004 /* 1:Software Reset */
-#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
-#define MAC_HaltReq 0x00000001 /* 1:Halt request */
+#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
+#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
+#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
+#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
+#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
+#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
+#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
+#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
+#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
+#define MAC_Reset 0x00000004 /* 1:Software Reset */
+#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
+#define MAC_HaltReq 0x00000001 /* 1:Halt request */
/* PROM_Ctl bit asign ------------------------------------------------------ */
-#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
-#define PROM_Read 0x00004000 /*10:Read operation */
-#define PROM_Write 0x00002000 /*01:Write operation */
-#define PROM_Erase 0x00006000 /*11:Erase operation */
- /*00:Enable or Disable Writting, */
- /* as specified in PROM_Addr. */
-#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
- /*00xxxx: disable */
+#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
+#define PROM_Read 0x00004000 /*10:Read operation */
+#define PROM_Write 0x00002000 /*01:Write operation */
+#define PROM_Erase 0x00006000 /*11:Erase operation */
+ /*00:Enable or Disable Writting, */
+ /* as specified in PROM_Addr. */
+#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
+ /*00xxxx: disable */
/* CAM_Ctl bit asign ------------------------------------------------------- */
-#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
-#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
- /* accept other */
-#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
-#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
-#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
+#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
+#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
+ /* accept other */
+#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
+#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
+#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
/* CAM_Ena bit asign ------------------------------------------------------- */
-#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
+#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
-#define CAM_Ena_Bit(index) (1<<(index))
+#define CAM_Ena_Bit(index) (1 << (index))
#define CAM_ENTRY_DESTINATION 0
#define CAM_ENTRY_SOURCE 1
#define CAM_ENTRY_MACCTL 20
/* Tx_Ctl bit asign -------------------------------------------------------- */
-#define Tx_En 0x00000001 /* 1:Transmit enable */
-#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
-#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
-#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
-#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
-#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
-#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
-#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
-#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
-#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
-#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
-#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
+#define Tx_En 0x00000001 /* 1:Transmit enable */
+#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
+#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
+#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
+#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
+#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
+#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
+#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
+#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
+#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
+#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
+#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
/* Tx_Stat bit asign ------------------------------------------------------- */
-#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
-#define Tx_ExColl 0x00000010 /* Excessive Collision */
-#define Tx_TXDefer 0x00000020 /* Transmit Defered */
-#define Tx_Paused 0x00000040 /* Transmit Paused */
-#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
-#define Tx_Under 0x00000100 /* Underrun */
-#define Tx_Defer 0x00000200 /* Deferral */
-#define Tx_NCarr 0x00000400 /* No Carrier */
-#define Tx_10Stat 0x00000800 /* 10Mbps Status */
-#define Tx_LateColl 0x00001000 /* Late Collision */
-#define Tx_TxPar 0x00002000 /* Tx Parity Error */
-#define Tx_Comp 0x00004000 /* Completion */
-#define Tx_Halted 0x00008000 /* Tx Halted */
-#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
+#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
+#define Tx_ExColl 0x00000010 /* Excessive Collision */
+#define Tx_TXDefer 0x00000020 /* Transmit Defered */
+#define Tx_Paused 0x00000040 /* Transmit Paused */
+#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
+#define Tx_Under 0x00000100 /* Underrun */
+#define Tx_Defer 0x00000200 /* Deferral */
+#define Tx_NCarr 0x00000400 /* No Carrier */
+#define Tx_10Stat 0x00000800 /* 10Mbps Status */
+#define Tx_LateColl 0x00001000 /* Late Collision */
+#define Tx_TxPar 0x00002000 /* Tx Parity Error */
+#define Tx_Comp 0x00004000 /* Completion */
+#define Tx_Halted 0x00008000 /* Tx Halted */
+#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
/* Rx_Ctl bit asign -------------------------------------------------------- */
-#define Rx_EnGood 0x00004000 /* 1:Enable Good */
-#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
-#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
-#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
-#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
-#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
-#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
-#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
-#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
-#define Rx_LongEn 0x00000004 /* 1:Long Enable */
-#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
-#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
+#define Rx_EnGood 0x00004000 /* 1:Enable Good */
+#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
+#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
+#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
+#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
+#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
+#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
+#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
+#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
+#define Rx_LongEn 0x00000004 /* 1:Long Enable */
+#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
+#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
/* Rx_Stat bit asign ------------------------------------------------------- */
-#define Rx_Halted 0x00008000 /* Rx Halted */
-#define Rx_Good 0x00004000 /* Rx Good */
-#define Rx_RxPar 0x00002000 /* Rx Parity Error */
- /* 0x00001000 not use */
-#define Rx_LongErr 0x00000800 /* Rx Long Error */
-#define Rx_Over 0x00000400 /* Rx Overflow */
-#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
-#define Rx_Align 0x00000100 /* Rx Alignment Error */
-#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
-#define Rx_IntRx 0x00000040 /* Rx Interrupt */
-#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
-
-#define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
+#define Rx_Halted 0x00008000 /* Rx Halted */
+#define Rx_Good 0x00004000 /* Rx Good */
+#define Rx_RxPar 0x00002000 /* Rx Parity Error */
+#define Rx_TypePkt 0x00001000 /* Rx Type Packet */
+#define Rx_LongErr 0x00000800 /* Rx Long Error */
+#define Rx_Over 0x00000400 /* Rx Overflow */
+#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
+#define Rx_Align 0x00000100 /* Rx Alignment Error */
+#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
+#define Rx_IntRx 0x00000040 /* Rx Interrupt */
+#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
+#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
+
+#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
/* Int_En bit asign -------------------------------------------------------- */
-#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
-#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
-#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
-#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
-#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
-#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
-#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
-#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
-#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
-#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
-#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
-#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
- /* Exhausted Enable */
+#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
+#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
+#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
+#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
+#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
+#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
+#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
+#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
+#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
+#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
+#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
+#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
+ /* Exhausted Enable */
/* Int_Src bit asign ------------------------------------------------------- */
-#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
-#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
-#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
-#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
-#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
-#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
-#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
-#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
-#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
-#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
-#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
-#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
-#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
-#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
-#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
+#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
+#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
+#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
+#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
+#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
+#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
+#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
+#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
+#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
+#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
+#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
+#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
+#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
+#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
+#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
/* MD_CA bit asign --------------------------------------------------------- */
-#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
-#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
-#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
+#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
+#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
+#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
/*
#define FD_ALIGN 16
/* Frame Descripter bit asign ---------------------------------------------- */
-#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
-#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
-#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
+#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
+#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
+#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
-#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
-#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
+#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
+#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
#define FD_FrmOpt_Packing 0x04000000 /* Rx only */
-#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
-#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
-#define FD_BDCnt_SHIFT 16
+#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
+#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
+#define FD_BDCnt_SHIFT 16
/* Buffer Descripter bit asign --------------------------------------------- */
-#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
-#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
-#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
-#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
-#define BD_RxBDID_SHIFT 16
+#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
+#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
+#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
+#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
+#define BD_RxBDID_SHIFT 16
#define BD_RxBDSeqN_SHIFT 24
/* Some useful constants. */
-#undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
-#ifdef NO_CHECK_CARRIER
-#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
- Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
- Tx_En) /* maybe 0x7b01 */
-#else
-#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
+#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
Tx_En) /* maybe 0x7b01 */
-#endif
+/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
- | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
+ | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
#define INT_EN_CMD (Int_NRAbtEn | \
Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
/* Tuning parameters */
#define DMA_BURST_SIZE 32
#define TX_THRESHOLD 1024
-#define TX_THRESHOLD_MAX 1536 /* used threshold with packet max byte for low pci transfer ability.*/
-#define TX_THRESHOLD_KEEP_LIMIT 10 /* setting threshold max value when overrun error occured this count. */
+/* used threshold with packet max byte for low pci transfer ability.*/
+#define TX_THRESHOLD_MAX 1536
+/* setting threshold max value when overrun error occured this count. */
+#define TX_THRESHOLD_KEEP_LIMIT 10
/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
-#ifdef TC35815_USE_PACKEDBUFFER
-#define FD_PAGE_NUM 2
-#define RX_BUF_NUM 8 /* >= 2 */
-#define RX_FD_NUM 250 /* >= 32 */
-#define TX_FD_NUM 128
-#define RX_BUF_SIZE PAGE_SIZE
-#else /* TC35815_USE_PACKEDBUFFER */
#define FD_PAGE_NUM 4
#define RX_BUF_NUM 128 /* < 256 */
#define RX_FD_NUM 256 /* >= 32 */
#if RX_CTL_CMD & Rx_LongEn
#define RX_BUF_SIZE PAGE_SIZE
#elif RX_CTL_CMD & Rx_StripCRC
-#define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 4 + 2, 32) /* +2: reserve */
+#define RX_BUF_SIZE \
+ L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
#else
-#define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 2, 32) /* +2: reserve */
+#define RX_BUF_SIZE \
+ L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
#endif
-#endif /* TC35815_USE_PACKEDBUFFER */
#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
#define NAPI_WEIGHT 16
int max_tx_qlen;
int tx_ints;
int rx_ints;
- int tx_underrun;
+ int tx_underrun;
} lstats;
/* Tx control lock. This protects the transmit buffer ring
* by this lock as well.
*/
spinlock_t lock;
+ spinlock_t rx_lock;
- struct mii_bus mii_bus;
+ struct mii_bus *mii_bus;
struct phy_device *phy_dev;
int duplex;
int speed;
/*
* Transmitting: Batch Mode.
* 1 BD in 1 TxFD.
- * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
- * 1 circular FD for Free Buffer List.
- * RX_BUF_NUM BD in Free Buffer FD.
- * One Free Buffer BD has PAGE_SIZE data buffer.
- * Or Non-Packing Mode.
+ * Receiving: Non-Packing Mode.
* 1 circular FD for Free Buffer List.
* RX_BUF_NUM BD in Free Buffer FD.
* One Free Buffer BD has ETH_FRAME_LEN data buffer.
*/
- void * fd_buf; /* for TxFD, RxFD, FrFD */
+ void *fd_buf; /* for TxFD, RxFD, FrFD */
dma_addr_t fd_buf_dma;
struct TxFD *tfd_base;
unsigned int tfd_start;
struct RxFD *rfd_limit;
struct RxFD *rfd_cur;
struct FrFD *fbl_ptr;
-#ifdef TC35815_USE_PACKEDBUFFER
- unsigned char fbl_curid;
- void * data_buf[RX_BUF_NUM]; /* packing */
- dma_addr_t data_buf_dma[RX_BUF_NUM];
- struct {
- struct sk_buff *skb;
- dma_addr_t skb_dma;
- } tx_skbs[TX_FD_NUM];
-#else
unsigned int fbl_count;
struct {
struct sk_buff *skb;
dma_addr_t skb_dma;
} tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
-#endif
u32 msg_enable;
enum tc35815_chiptype chiptype;
};
return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
}
#endif
-#ifdef TC35815_USE_PACKEDBUFFER
-static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
-{
- int i;
- for (i = 0; i < RX_BUF_NUM; i++) {
- if (bus >= lp->data_buf_dma[i] &&
- bus < lp->data_buf_dma[i] + PAGE_SIZE)
- return (void *)((u8 *)lp->data_buf[i] +
- (bus - lp->data_buf_dma[i]));
- }
- return NULL;
-}
-
-#define TC35815_DMA_SYNC_ONDEMAND
-static void* alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
-{
-#ifdef TC35815_DMA_SYNC_ONDEMAND
- void *buf;
- /* pci_map + pci_dma_sync will be more effective than
- * pci_alloc_consistent on some archs. */
- if ((buf = (void *)__get_free_page(GFP_ATOMIC)) == NULL)
- return NULL;
- *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
- PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(*dma_handle)) {
- free_page((unsigned long)buf);
- return NULL;
- }
- return buf;
-#else
- return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
-#endif
-}
-
-static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
-{
-#ifdef TC35815_DMA_SYNC_ONDEMAND
- pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
- free_page((unsigned long)buf);
-#else
- pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
-#endif
-}
-#else /* TC35815_USE_PACKEDBUFFER */
static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
struct pci_dev *hwdev,
dma_addr_t *dma_handle)
return NULL;
*dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(*dma_handle)) {
+ if (pci_dma_mapping_error(hwdev, *dma_handle)) {
dev_kfree_skb_any(skb);
return NULL;
}
PCI_DMA_FROMDEVICE);
dev_kfree_skb_any(skb);
}
-#endif /* TC35815_USE_PACKEDBUFFER */
/* Index to functions, as function prototypes. */
static int tc35815_open(struct net_device *dev);
static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
-#ifdef TC35815_NAPI
static int tc35815_rx(struct net_device *dev, int limit);
static int tc35815_poll(struct napi_struct *napi, int budget);
-#else
-static void tc35815_rx(struct net_device *dev);
-#endif
static void tc35815_txdone(struct net_device *dev);
static int tc35815_close(struct net_device *dev);
static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
static void tc35815_set_multicast_list(struct net_device *dev);
-static void tc35815_tx_timeout(struct net_device *dev);
+static void tc35815_tx_timeout(struct net_device *dev);
static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
#ifdef CONFIG_NET_POLL_CONTROLLER
static void tc35815_poll_controller(struct net_device *dev);
static const struct ethtool_ops tc35815_ethtool_ops;
/* Example routines you must write ;->. */
-static void tc35815_chip_reset(struct net_device *dev);
-static void tc35815_chip_init(struct net_device *dev);
+static void tc35815_chip_reset(struct net_device *dev);
+static void tc35815_chip_init(struct net_device *dev);
#ifdef DEBUG
static void panic_queues(struct net_device *dev);
struct net_device *dev = bus->priv;
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
- unsigned long timeout = jiffies + 10;
+ unsigned long timeout = jiffies + HZ;
tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
+ udelay(12); /* it takes 32 x 400ns at least */
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
if (time_after(jiffies, timeout))
return -EIO;
struct net_device *dev = bus->priv;
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
- unsigned long timeout = jiffies + 10;
+ unsigned long timeout = jiffies + HZ;
tc_writel(val, &tr->MD_Data);
tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
&tr->MD_CA);
+ udelay(12); /* it takes 32 x 400ns at least */
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
if (time_after(jiffies, timeout))
return -EIO;
* TX4939 PCFG.SPEEDn bit will be changed on
* NETDEV_CHANGE event.
*/
-
-#if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
/*
* WORKAROUND: enable LostCrS only if half duplex
* operation.
lp->chiptype != TC35815_TX4939)
tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
&tr->Tx_Ctl);
-#endif
lp->speed = phydev->speed;
lp->duplex = phydev->duplex;
if (phydev->link != lp->link) {
if (phydev->link) {
-#ifdef WORKAROUND_100HALF_PROMISC
/* delayed promiscuous enabling */
if (dev->flags & IFF_PROMISC)
tc35815_set_multicast_list(dev);
-#endif
- netif_schedule(dev);
} else {
lp->speed = 0;
lp->duplex = -1;
if (status_change && netif_msg_link(lp)) {
phy_print_status(phydev);
-#ifdef DEBUG
- printk(KERN_DEBUG
- "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
- dev->name,
- phy_read(phydev, MII_BMCR),
- phy_read(phydev, MII_BMSR),
- phy_read(phydev, MII_LPA));
-#endif
+ pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
+ dev->name,
+ phy_read(phydev, MII_BMCR),
+ phy_read(phydev, MII_BMSR),
+ phy_read(phydev, MII_LPA));
}
}
/* find the first phy */
for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
- if (lp->mii_bus.phy_map[phy_addr]) {
+ if (lp->mii_bus->phy_map[phy_addr]) {
if (phydev) {
printk(KERN_ERR "%s: multiple PHYs found\n",
dev->name);
return -EINVAL;
}
- phydev = lp->mii_bus.phy_map[phy_addr];
+ phydev = lp->mii_bus->phy_map[phy_addr];
break;
}
}
}
/* attach the mac to the phy */
- phydev = phy_connect(dev, phydev->dev.bus_id,
+ phydev = phy_connect(dev, dev_name(&phydev->dev),
&tc_handle_link_change, 0,
lp->chiptype == TC35815_TX4939 ?
PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
}
printk(KERN_INFO "%s: attached PHY driver [%s] "
"(mii_bus:phy_addr=%s, id=%x)\n",
- dev->name, phydev->drv->name, phydev->dev.bus_id,
+ dev->name, phydev->drv->name, dev_name(&phydev->dev),
phydev->phy_id);
/* mask with MAC supported features */
int err;
int i;
- lp->mii_bus.name = "tc35815_mii_bus";
- lp->mii_bus.read = tc_mdio_read;
- lp->mii_bus.write = tc_mdio_write;
- lp->mii_bus.id = (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn;
- lp->mii_bus.priv = dev;
- lp->mii_bus.dev = &lp->pci_dev->dev;
- lp->mii_bus.irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
- if (!lp->mii_bus.irq) {
+ lp->mii_bus = mdiobus_alloc();
+ if (lp->mii_bus == NULL) {
err = -ENOMEM;
goto err_out;
}
+ lp->mii_bus->name = "tc35815_mii_bus";
+ lp->mii_bus->read = tc_mdio_read;
+ lp->mii_bus->write = tc_mdio_write;
+ snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+ (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
+ lp->mii_bus->priv = dev;
+ lp->mii_bus->parent = &lp->pci_dev->dev;
+ lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+ if (!lp->mii_bus->irq) {
+ err = -ENOMEM;
+ goto err_out_free_mii_bus;
+ }
+
for (i = 0; i < PHY_MAX_ADDR; i++)
- lp->mii_bus.irq[i] = PHY_POLL;
+ lp->mii_bus->irq[i] = PHY_POLL;
- err = mdiobus_register(&lp->mii_bus);
+ err = mdiobus_register(lp->mii_bus);
if (err)
goto err_out_free_mdio_irq;
err = tc_mii_probe(dev);
return 0;
err_out_unregister_bus:
- mdiobus_unregister(&lp->mii_bus);
+ mdiobus_unregister(lp->mii_bus);
err_out_free_mdio_irq:
- kfree(lp->mii_bus.irq);
+ kfree(lp->mii_bus->irq);
+err_out_free_mii_bus:
+ mdiobus_free(lp->mii_bus);
err_out:
return err;
}
}
#endif
-static int __devinit tc35815_init_dev_addr (struct net_device *dev)
+static int __devinit tc35815_init_dev_addr(struct net_device *dev)
{
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
return 0;
}
-static int __devinit tc35815_init_one (struct pci_dev *pdev,
- const struct pci_device_id *ent)
+static const struct net_device_ops tc35815_netdev_ops = {
+ .ndo_open = tc35815_open,
+ .ndo_stop = tc35815_close,
+ .ndo_start_xmit = tc35815_send_packet,
+ .ndo_get_stats = tc35815_get_stats,
+ .ndo_set_multicast_list = tc35815_set_multicast_list,
+ .ndo_tx_timeout = tc35815_tx_timeout,
+ .ndo_do_ioctl = tc35815_ioctl,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = tc35815_poll_controller,
+#endif
+};
+
+static int __devinit tc35815_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
{
void __iomem *ioaddr = NULL;
struct net_device *dev;
struct tc35815_local *lp;
int rc;
- DECLARE_MAC_BUF(mac);
static int printed_version;
if (!printed_version++) {
}
/* dev zeroed in alloc_etherdev */
- dev = alloc_etherdev (sizeof (*lp));
+ dev = alloc_etherdev(sizeof(*lp));
if (dev == NULL) {
dev_err(&pdev->dev, "unable to alloc new ethernet\n");
return -ENOMEM;
ioaddr = pcim_iomap_table(pdev)[1];
/* Initialize the device structure. */
- dev->open = tc35815_open;
- dev->hard_start_xmit = tc35815_send_packet;
- dev->stop = tc35815_close;
- dev->get_stats = tc35815_get_stats;
- dev->set_multicast_list = tc35815_set_multicast_list;
- dev->do_ioctl = tc35815_ioctl;
+ dev->netdev_ops = &tc35815_netdev_ops;
dev->ethtool_ops = &tc35815_ethtool_ops;
- dev->tx_timeout = tc35815_tx_timeout;
dev->watchdog_timeo = TC35815_TX_TIMEOUT;
-#ifdef TC35815_NAPI
netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
-#endif
-#ifdef CONFIG_NET_POLL_CONTROLLER
- dev->poll_controller = tc35815_poll_controller;
-#endif
dev->irq = pdev->irq;
- dev->base_addr = (unsigned long) ioaddr;
+ dev->base_addr = (unsigned long)ioaddr;
INIT_WORK(&lp->restart_work, tc35815_restart_work);
spin_lock_init(&lp->lock);
+ spin_lock_init(&lp->rx_lock);
lp->pci_dev = pdev;
lp->chiptype = ent->driver_data;
random_ether_addr(dev->dev_addr);
}
- rc = register_netdev (dev);
+ rc = register_netdev(dev);
if (rc)
goto err_out;
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
- printk(KERN_INFO "%s: %s at 0x%lx, %s, IRQ %d\n",
+ printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
dev->name,
chip_info[ent->driver_data].name,
dev->base_addr,
- print_mac(mac, dev->dev_addr),
+ dev->dev_addr,
dev->irq);
rc = tc_mii_init(dev);
err_out_unregister:
unregister_netdev(dev);
err_out:
- free_netdev (dev);
+ free_netdev(dev);
return rc;
}
-static void __devexit tc35815_remove_one (struct pci_dev *pdev)
+static void __devexit tc35815_remove_one(struct pci_dev *pdev)
{
- struct net_device *dev = pci_get_drvdata (pdev);
+ struct net_device *dev = pci_get_drvdata(pdev);
struct tc35815_local *lp = netdev_priv(dev);
phy_disconnect(lp->phy_dev);
- mdiobus_unregister(&lp->mii_bus);
- kfree(lp->mii_bus.irq);
- unregister_netdev (dev);
- free_netdev (dev);
-
- pci_set_drvdata (pdev, NULL);
+ mdiobus_unregister(lp->mii_bus);
+ kfree(lp->mii_bus->irq);
+ mdiobus_free(lp->mii_bus);
+ unregister_netdev(dev);
+ free_netdev(dev);
+ pci_set_drvdata(pdev, NULL);
}
static int
sizeof(struct TxFD) * TX_FD_NUM >
PAGE_SIZE * FD_PAGE_NUM);
- if ((lp->fd_buf = pci_alloc_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, &lp->fd_buf_dma)) == 0)
+ lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
+ PAGE_SIZE * FD_PAGE_NUM,
+ &lp->fd_buf_dma);
+ if (!lp->fd_buf)
return -ENOMEM;
for (i = 0; i < RX_BUF_NUM; i++) {
-#ifdef TC35815_USE_PACKEDBUFFER
- if ((lp->data_buf[i] = alloc_rxbuf_page(lp->pci_dev, &lp->data_buf_dma[i])) == NULL) {
- while (--i >= 0) {
- free_rxbuf_page(lp->pci_dev,
- lp->data_buf[i],
- lp->data_buf_dma[i]);
- lp->data_buf[i] = NULL;
- }
- pci_free_consistent(lp->pci_dev,
- PAGE_SIZE * FD_PAGE_NUM,
- lp->fd_buf,
- lp->fd_buf_dma);
- lp->fd_buf = NULL;
- return -ENOMEM;
- }
-#else
lp->rx_skbs[i].skb =
alloc_rxbuf_skb(dev, lp->pci_dev,
&lp->rx_skbs[i].skb_dma);
lp->fd_buf = NULL;
return -ENOMEM;
}
-#endif
}
printk(KERN_DEBUG "%s: FD buf %p DataBuf",
dev->name, lp->fd_buf);
-#ifdef TC35815_USE_PACKEDBUFFER
- printk(" DataBuf");
- for (i = 0; i < RX_BUF_NUM; i++)
- printk(" %p", lp->data_buf[i]);
-#endif
printk("\n");
} else {
- for (i = 0; i < FD_PAGE_NUM; i++) {
- clear_page((void *)((unsigned long)lp->fd_buf + i * PAGE_SIZE));
- }
+ for (i = 0; i < FD_PAGE_NUM; i++)
+ clear_page((void *)((unsigned long)lp->fd_buf +
+ i * PAGE_SIZE));
}
fd_addr = (unsigned long)lp->fd_buf;
/* Free Descriptors (for Receive) */
lp->rfd_base = (struct RxFD *)fd_addr;
fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
- for (i = 0; i < RX_FD_NUM; i++) {
+ for (i = 0; i < RX_FD_NUM; i++)
lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
- }
lp->rfd_cur = lp->rfd_base;
lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
lp->fbl_ptr = (struct FrFD *)fd_addr;
lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
-#ifndef TC35815_USE_PACKEDBUFFER
/*
* move all allocated skbs to head of rx_skbs[] array.
* fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
lp->fbl_count++;
}
}
-#endif
for (i = 0; i < RX_BUF_NUM; i++) {
-#ifdef TC35815_USE_PACKEDBUFFER
- lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
-#else
if (i >= lp->fbl_count) {
lp->fbl_ptr->bd[i].BuffData = 0;
lp->fbl_ptr->bd[i].BDCtl = 0;
}
lp->fbl_ptr->bd[i].BuffData =
cpu_to_le32(lp->rx_skbs[i].skb_dma);
-#endif
/* BDID is index of FrFD.bd[] */
lp->fbl_ptr->bd[i].BDCtl =
cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
RX_BUF_SIZE);
}
-#ifdef TC35815_USE_PACKEDBUFFER
- lp->fbl_curid = 0;
-#endif
printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
lp->fbl_ptr = NULL;
for (i = 0; i < RX_BUF_NUM; i++) {
-#ifdef TC35815_USE_PACKEDBUFFER
- if (lp->data_buf[i]) {
- free_rxbuf_page(lp->pci_dev,
- lp->data_buf[i], lp->data_buf_dma[i]);
- lp->data_buf[i] = NULL;
- }
-#else
if (lp->rx_skbs[i].skb) {
free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
lp->rx_skbs[i].skb_dma);
lp->rx_skbs[i].skb = NULL;
}
-#endif
}
if (lp->fd_buf) {
pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
le32_to_cpu(fd->fd.FDStat),
le32_to_cpu(fd->fd.FDCtl));
if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
- return 0;
+ return 0;
printk("BD: ");
for (i = 0; i < bd_count; i++)
printk(" %08x %08x",
return bd_count;
}
-#if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
+#ifdef DEBUG
static void
dump_frfd(struct FrFD *fd)
{
le32_to_cpu(fd->bd[i].BDCtl));
printk("\n");
}
-#endif
-#ifdef DEBUG
static void
panic_queues(struct net_device *dev)
{
static void print_eth(const u8 *add)
{
- DECLARE_MAC_BUF(mac);
-
printk(KERN_DEBUG "print_eth(%p)\n", add);
- printk(KERN_DEBUG " %s =>", print_mac(mac, add + 6));
- printk(KERN_CONT " %s : %02x%02x\n",
- print_mac(mac, add), add[12], add[13]);
+ printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
+ add + 6, add, add[12], add[13]);
}
static int tc35815_tx_full(struct net_device *dev)
printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
}
+ spin_lock_bh(&lp->rx_lock);
spin_lock_irq(&lp->lock);
tc35815_chip_reset(dev);
tc35815_clear_queues(dev);
/* Reconfigure CAM again since tc35815_chip_init() initialize it. */
tc35815_set_multicast_list(dev);
spin_unlock_irq(&lp->lock);
+ spin_unlock_bh(&lp->rx_lock);
netif_wake_queue(dev);
}
struct tc35815_local *lp = netdev_priv(dev);
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
+ unsigned long flags;
/* disable interrupts */
+ spin_lock_irqsave(&lp->lock, flags);
tc_writel(0, &tr->Int_En);
tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
schedule_work(&lp->restart_work);
+ spin_unlock_irqrestore(&lp->lock, flags);
}
static void tc35815_tx_timeout(struct net_device *dev)
* This is used if the interrupt line can turned off (shared).
* See 3c503.c for an example of selecting the IRQ at config-time.
*/
- if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED, dev->name, dev)) {
+ if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
+ dev->name, dev))
return -EAGAIN;
- }
tc35815_chip_reset(dev);
return -EAGAIN;
}
-#ifdef TC35815_NAPI
napi_enable(&lp->napi);
-#endif
/* Reset the hardware here. Don't forget to set the station address. */
spin_lock_irq(&lp->lock);
tc35815_chip_init(dev);
spin_unlock_irq(&lp->lock);
+ netif_carrier_off(dev);
/* schedule a link state check */
phy_start(lp->phy_dev);
(struct tc35815_regs __iomem *)dev->base_addr;
/* Start DMA Transmitter. */
txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
-#ifdef GATHER_TXINT
txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
-#endif
if (netif_msg_tx_queued(lp)) {
printk("%s: starting TxFD.\n", dev->name);
dump_txfd(txfd);
}
lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
- dev->trans_start = jiffies;
-
/* If we just used up the very last entry in the
* TX ring on this device, tell the queueing
* layer to send no more.
*/
spin_unlock_irqrestore(&lp->lock, flags);
- return 0;
+ return NETDEV_TX_OK;
}
#define FATAL_ERROR_INT \
tc35815_schedule_restart(dev);
}
-#ifdef TC35815_NAPI
static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
-#else
-static int tc35815_do_interrupt(struct net_device *dev, u32 status)
-#endif
{
struct tc35815_local *lp = netdev_priv(dev);
- struct tc35815_regs __iomem *tr =
- (struct tc35815_regs __iomem *)dev->base_addr;
int ret = -1;
/* Fatal errors... */
}
/* recoverable errors */
if (status & Int_IntFDAEx) {
- /* disable FDAEx int. (until we make rooms...) */
- tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
- printk(KERN_WARNING
- "%s: Free Descriptor Area Exhausted (%#x).\n",
- dev->name, status);
+ if (netif_msg_rx_err(lp))
+ dev_warn(&dev->dev,
+ "Free Descriptor Area Exhausted (%#x).\n",
+ status);
dev->stats.rx_dropped++;
ret = 0;
}
if (status & Int_IntBLEx) {
- /* disable BLEx int. (until we make rooms...) */
- tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
- printk(KERN_WARNING
- "%s: Buffer List Exhausted (%#x).\n",
- dev->name, status);
+ if (netif_msg_rx_err(lp))
+ dev_warn(&dev->dev,
+ "Buffer List Exhausted (%#x).\n",
+ status);
dev->stats.rx_dropped++;
ret = 0;
}
if (status & Int_IntExBD) {
- printk(KERN_WARNING
- "%s: Excessive Buffer Descriptiors (%#x).\n",
- dev->name, status);
+ if (netif_msg_rx_err(lp))
+ dev_warn(&dev->dev,
+ "Excessive Buffer Descriptiors (%#x).\n",
+ status);
dev->stats.rx_length_errors++;
ret = 0;
}
/* normal notification */
if (status & Int_IntMacRx) {
/* Got a packet(s). */
-#ifdef TC35815_NAPI
ret = tc35815_rx(dev, limit);
-#else
- tc35815_rx(dev);
- ret = 0;
-#endif
lp->lstats.rx_ints++;
}
if (status & Int_IntMacTx) {
/* Transmit complete. */
lp->lstats.tx_ints++;
+ spin_lock_irq(&lp->lock);
tc35815_txdone(dev);
- netif_wake_queue(dev);
- ret = 0;
+ spin_unlock_irq(&lp->lock);
+ if (ret < 0)
+ ret = 0;
}
return ret;
}
struct tc35815_local *lp = netdev_priv(dev);
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
-#ifdef TC35815_NAPI
u32 dmactl = tc_readl(&tr->DMA_Ctl);
if (!(dmactl & DMA_IntMask)) {
/* disable interrupts */
tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
- if (netif_rx_schedule_prep(dev, &lp->napi))
- __netif_rx_schedule(dev, &lp->napi);
+ if (napi_schedule_prep(&lp->napi))
+ __napi_schedule(&lp->napi);
else {
printk(KERN_ERR "%s: interrupt taken in poll\n",
dev->name);
return IRQ_HANDLED;
}
return IRQ_NONE;
-#else
- int handled;
- u32 status;
-
- spin_lock(&lp->lock);
- status = tc_readl(&tr->Int_Src);
- tc_writel(status, &tr->Int_Src); /* write to clear */
- handled = tc35815_do_interrupt(dev, status);
- (void)tc_readl(&tr->Int_Src); /* flush */
- spin_unlock(&lp->lock);
- return IRQ_RETVAL(handled >= 0);
-#endif /* TC35815_NAPI */
}
#ifdef CONFIG_NET_POLL_CONTROLLER
#endif
/* We have a good packet(s), get it/them out of the buffers. */
-#ifdef TC35815_NAPI
static int
tc35815_rx(struct net_device *dev, int limit)
-#else
-static void
-tc35815_rx(struct net_device *dev)
-#endif
{
struct tc35815_local *lp = netdev_priv(dev);
unsigned int fdctl;
int i;
- int buf_free_count = 0;
- int fd_free_count = 0;
-#ifdef TC35815_NAPI
int received = 0;
-#endif
while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
struct RxFD *next_rfd;
#endif
#if (RX_CTL_CMD & Rx_StripCRC) == 0
- pkt_len -= 4;
+ pkt_len -= ETH_FCS_LEN;
#endif
if (netif_msg_rx_status(lp))
struct sk_buff *skb;
unsigned char *data;
int cur_bd;
-#ifdef TC35815_USE_PACKEDBUFFER
- int offset;
-#endif
-#ifdef TC35815_NAPI
if (--limit < 0)
break;
-#endif
-#ifdef TC35815_USE_PACKEDBUFFER
- BUG_ON(bd_count > 2);
- skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
- if (skb == NULL) {
- printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
- dev->name);
- dev->stats.rx_dropped++;
- break;
- }
- skb_reserve(skb, 2); /* 16 bit alignment */
-
- data = skb_put(skb, pkt_len);
-
- /* copy from receive buffer */
- cur_bd = 0;
- offset = 0;
- while (offset < pkt_len && cur_bd < bd_count) {
- int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
- BD_BuffLength_MASK;
- dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
- void *rxbuf = rxbuf_bus_to_virt(lp, dma);
- if (offset + len > pkt_len)
- len = pkt_len - offset;
-#ifdef TC35815_DMA_SYNC_ONDEMAND
- pci_dma_sync_single_for_cpu(lp->pci_dev,
- dma, len,
- PCI_DMA_FROMDEVICE);
-#endif
- memcpy(data + offset, rxbuf, len);
-#ifdef TC35815_DMA_SYNC_ONDEMAND
- pci_dma_sync_single_for_device(lp->pci_dev,
- dma, len,
- PCI_DMA_FROMDEVICE);
-#endif
- offset += len;
- cur_bd++;
- }
-#else /* TC35815_USE_PACKEDBUFFER */
BUG_ON(bd_count > 1);
cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
& BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
skb = lp->rx_skbs[cur_bd].skb;
prefetch(skb->data);
lp->rx_skbs[cur_bd].skb = NULL;
- lp->fbl_count--;
pci_unmap_single(lp->pci_dev,
lp->rx_skbs[cur_bd].skb_dma,
RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
- if (!HAVE_DMA_RXALIGN(lp))
- memmove(skb->data, skb->data - 2, pkt_len);
+ if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
+ memmove(skb->data, skb->data - NET_IP_ALIGN,
+ pkt_len);
data = skb_put(skb, pkt_len);
-#endif /* TC35815_USE_PACKEDBUFFER */
if (netif_msg_pktdata(lp))
print_eth(data);
skb->protocol = eth_type_trans(skb, dev);
-#ifdef TC35815_NAPI
netif_receive_skb(skb);
received++;
-#else
- netif_rx(skb);
-#endif
- dev->last_rx = jiffies;
dev->stats.rx_packets++;
dev->stats.rx_bytes += pkt_len;
} else {
dev->stats.rx_errors++;
- printk(KERN_DEBUG "%s: Rx error (status %x)\n",
- dev->name, status & Rx_Stat_Mask);
+ if (netif_msg_rx_err(lp))
+ dev_info(&dev->dev, "Rx error (status %x)\n",
+ status & Rx_Stat_Mask);
/* WORKAROUND: LongErr and CRCErr means Overflow. */
if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
status &= ~(Rx_LongErr|Rx_CRCErr);
BUG_ON(id >= RX_BUF_NUM);
#endif
/* free old buffers */
-#ifdef TC35815_USE_PACKEDBUFFER
- while (lp->fbl_curid != id)
-#else
+ lp->fbl_count--;
while (lp->fbl_count < RX_BUF_NUM)
-#endif
{
-#ifdef TC35815_USE_PACKEDBUFFER
- unsigned char curid = lp->fbl_curid;
-#else
unsigned char curid =
(id + 1 + lp->fbl_count) % RX_BUF_NUM;
-#endif
struct BDesc *bd = &lp->fbl_ptr->bd[curid];
#ifdef DEBUG
bdctl = le32_to_cpu(bd->BDCtl);
}
#endif
/* pass BD to controller */
-#ifndef TC35815_USE_PACKEDBUFFER
if (!lp->rx_skbs[curid].skb) {
lp->rx_skbs[curid].skb =
alloc_rxbuf_skb(dev,
break; /* try on next reception */
bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
}
-#endif /* TC35815_USE_PACKEDBUFFER */
/* Note: BDLength was modified by chip. */
bd->BDCtl = cpu_to_le32(BD_CownsBD |
(curid << BD_RxBDID_SHIFT) |
RX_BUF_SIZE);
-#ifdef TC35815_USE_PACKEDBUFFER
- lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
- if (netif_msg_rx_status(lp)) {
- printk("%s: Entering new FBD %d\n",
- dev->name, lp->fbl_curid);
- dump_frfd(lp->fbl_ptr);
- }
-#else
lp->fbl_count++;
-#endif
- buf_free_count++;
}
}
#endif
lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
lp->rfd_cur++;
- fd_free_count++;
}
if (lp->rfd_cur > lp->rfd_limit)
lp->rfd_cur = lp->rfd_base;
#endif
}
- /* re-enable BL/FDA Exhaust interrupts. */
- if (fd_free_count) {
- struct tc35815_regs __iomem *tr =
- (struct tc35815_regs __iomem *)dev->base_addr;
- u32 en, en_old = tc_readl(&tr->Int_En);
- en = en_old | Int_FDAExEn;
- if (buf_free_count)
- en |= Int_BLExEn;
- if (en != en_old)
- tc_writel(en, &tr->Int_En);
- }
-#ifdef TC35815_NAPI
return received;
-#endif
}
-#ifdef TC35815_NAPI
static int tc35815_poll(struct napi_struct *napi, int budget)
{
struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
int received = 0, handled;
u32 status;
- spin_lock(&lp->lock);
+ spin_lock(&lp->rx_lock);
status = tc_readl(&tr->Int_Src);
do {
- tc_writel(status, &tr->Int_Src); /* write to clear */
-
- handled = tc35815_do_interrupt(dev, status, limit);
+ /* BLEx, FDAEx will be cleared later */
+ tc_writel(status & ~(Int_BLEx | Int_FDAEx),
+ &tr->Int_Src); /* write to clear */
+
+ handled = tc35815_do_interrupt(dev, status, budget - received);
+ if (status & (Int_BLEx | Int_FDAEx))
+ tc_writel(status & (Int_BLEx | Int_FDAEx),
+ &tr->Int_Src);
if (handled >= 0) {
received += handled;
if (received >= budget)
}
status = tc_readl(&tr->Int_Src);
} while (status);
- spin_unlock(&lp->lock);
+ spin_unlock(&lp->rx_lock);
if (received < budget) {
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
/* enable interrupts */
tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
}
return received;
}
-#endif
-#ifdef NO_CHECK_CARRIER
-#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
-#else
#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
-#endif
static void
tc35815_check_tx_stat(struct net_device *dev, int status)
if (status & Tx_TxColl_MASK)
dev->stats.collisions += status & Tx_TxColl_MASK;
-#ifndef NO_CHECK_CARRIER
/* TX4939 does not have NCarr */
if (lp->chiptype == TC35815_TX4939)
status &= ~Tx_NCarr;
-#ifdef WORKAROUND_LOSTCAR
/* WORKAROUND: ignore LostCrS in full duplex operation */
if (!lp->link || lp->duplex == DUPLEX_FULL)
status &= ~Tx_NCarr;
-#endif
-#endif
if (!(status & TX_STA_ERR)) {
/* no error. */
dev->stats.tx_fifo_errors++;
msg = "Excessive Deferral.";
}
-#ifndef NO_CHECK_CARRIER
if (status & Tx_NCarr) {
dev->stats.tx_carrier_errors++;
msg = "Lost Carrier Sense.";
}
-#endif
if (status & Tx_LateColl) {
dev->stats.tx_aborted_errors++;
msg = "Late Collision.";
pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
lp->tx_skbs[lp->tfd_end].skb = NULL;
lp->tx_skbs[lp->tfd_end].skb_dma = 0;
-#ifdef TC35815_NAPI
dev_kfree_skb_any(skb);
-#else
- dev_kfree_skb_irq(skb);
-#endif
}
txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
- struct TxFD* txhead = &lp->tfd_base[head];
+ struct TxFD *txhead = &lp->tfd_base[head];
int qlen = (lp->tfd_start + TX_FD_NUM
- lp->tfd_end) % TX_FD_NUM;
/* start DMA Transmitter again */
txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
-#ifdef GATHER_TXINT
txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
-#endif
if (netif_msg_tx_queued(lp)) {
printk("%s: start TxFD on queue.\n",
dev->name);
* condition, and space has now been made available,
* wake up the queue.
*/
- if (netif_queue_stopped(dev) && ! tc35815_tx_full(dev))
+ if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
netif_wake_queue(dev);
}
struct tc35815_local *lp = netdev_priv(dev);
netif_stop_queue(dev);
-#ifdef TC35815_NAPI
napi_disable(&lp->napi);
-#endif
if (lp->phy_dev)
phy_stop(lp->phy_dev);
cancel_work_sync(&lp->restart_work);
(struct tc35815_regs __iomem *)dev->base_addr;
if (netif_running(dev))
/* Update the statistics from the device registers. */
- dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
+ dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
return &dev->stats;
}
int cam_index = index * 6;
u32 cam_data;
u32 saved_addr;
- DECLARE_MAC_BUF(mac);
saved_addr = tc_readl(&tr->CAM_Adr);
if (netif_msg_hw(lp))
- printk(KERN_DEBUG "%s: CAM %d: %s\n",
- dev->name, index, print_mac(mac, addr));
+ printk(KERN_DEBUG "%s: CAM %d: %pM\n",
+ dev->name, index, addr);
if (index & 1) {
/* read modify write */
tc_writel(cam_index - 2, &tr->CAM_Adr);
struct tc35815_regs __iomem *tr =
(struct tc35815_regs __iomem *)dev->base_addr;
- if (dev->flags&IFF_PROMISC)
- {
-#ifdef WORKAROUND_100HALF_PROMISC
+ if (dev->flags & IFF_PROMISC) {
/* With some (all?) 100MHalf HUB, controller will hang
* if we enabled promiscuous mode before linkup... */
struct tc35815_local *lp = netdev_priv(dev);
if (!lp->link)
return;
-#endif
/* Enable promiscuous mode */
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
- }
- else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
- {
+ } else if ((dev->flags & IFF_ALLMULTI) ||
+ netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
/* CAM 0, 1, 20 are reserved. */
/* Disable promiscuous mode, use normal mode. */
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
- }
- else if(dev->mc_count)
- {
- struct dev_mc_list* cur_addr = dev->mc_list;
+ } else if (!netdev_mc_empty(dev)) {
+ struct netdev_hw_addr *ha;
int i;
int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
tc_writel(0, &tr->CAM_Ctl);
/* Walk the address list, and load the filter */
- for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
- if (!cur_addr)
- break;
+ i = 0;
+ netdev_for_each_mc_addr(ha, dev) {
/* entry 0,1 is reserved. */
- tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
+ tc35815_set_cam_entry(dev, i + 2, ha->addr);
ena_bits |= CAM_Ena_Bit(i + 2);
+ i++;
}
tc_writel(ena_bits, &tr->CAM_Ena);
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
- }
- else {
+ } else {
tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
}
tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
else
tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
-#ifdef TC35815_USE_PACKEDBUFFER
- tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
-#else
- tc_writel(ETH_ZLEN, &tr->RxFragSize);
-#endif
tc_writel(0, &tr->TxPollCtr); /* Batch mode */
tc_writel(TX_THRESHOLD, &tr->TxThrsh);
tc_writel(INT_EN_CMD, &tr->Int_En);
tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
/* start MAC transmitter */
-#ifndef NO_CHECK_CARRIER
/* TX4939 does not have EnLCarr */
if (lp->chiptype == TC35815_TX4939)
txctl &= ~Tx_EnLCarr;
-#ifdef WORKAROUND_LOSTCAR
/* WORKAROUND: ignore LostCrS in full duplex operation */
if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
txctl &= ~Tx_EnLCarr;
-#endif
-#endif /* !NO_CHECK_CARRIER */
-#ifdef GATHER_TXINT
- txctl &= ~Tx_EnComp; /* disable global tx completion int. */
-#endif
tc_writel(txctl, &tr->Tx_Ctl);
}
return 0;
pci_set_power_state(pdev, PCI_D0);
tc35815_restart(dev);
+ netif_carrier_off(dev);
if (lp->phy_dev)
phy_start(lp->phy_dev);
netif_device_attach(dev);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff