. Authors
. Erik Stahlman <erik@vt.edu>
. Daris A Nevil <dnevil@snmc.com>
- . Nicolas Pitre <nico@cam.org>
+ . Nicolas Pitre <nico@fluxnic.net>
.
---------------------------------------------------------------------------*/
#ifndef _SMC91X_H_
#define _SMC91X_H_
+#include <linux/smc91x.h>
/*
* Define your architecture specific bus configuration parameters here.
*/
-#if defined(CONFIG_ARCH_LUBBOCK)
+#if defined(CONFIG_ARCH_LUBBOCK) ||\
+ defined(CONFIG_MACH_MAINSTONE) ||\
+ defined(CONFIG_MACH_ZYLONITE) ||\
+ defined(CONFIG_MACH_LITTLETON) ||\
+ defined(CONFIG_MACH_ZYLONITE2) ||\
+ defined(CONFIG_ARCH_VIPER) ||\
+ defined(CONFIG_MACH_STARGATE2)
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT 0
+#include <asm/mach-types.h>
+
+/* Now the bus width is specified in the platform data
+ * pretend here to support all I/O access types
+ */
+#define SMC_CAN_USE_8BIT 1
#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
+#define SMC_CAN_USE_32BIT 1
#define SMC_NOWAIT 1
-/* The first two address lines aren't connected... */
-#define SMC_IO_SHIFT 2
+#define SMC_IO_SHIFT (lp->io_shift)
+#define SMC_inb(a, r) readb((a) + (r))
#define SMC_inw(a, r) readw((a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
+#define SMC_inl(a, r) readl((a) + (r))
+#define SMC_outb(v, a, r) writeb(v, (a) + (r))
+#define SMC_outl(v, a, r) writel(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
+#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
-#elif defined(CONFIG_BLACKFIN)
-
-#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
-#define RPC_LSA_DEFAULT RPC_LED_100_10
-#define RPC_LSB_DEFAULT RPC_LED_TX_RX
-
-# if defined (CONFIG_BFIN561_EZKIT)
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 1
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-#define SMC_USE_BFIN_DMA 0
-
+/* We actually can't write halfwords properly if not word aligned */
+static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
+{
+ if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
+ unsigned int v = val << 16;
+ v |= readl(ioaddr + (reg & ~2)) & 0xffff;
+ writel(v, ioaddr + (reg & ~2));
+ } else {
+ writew(val, ioaddr + reg);
+ }
+}
-#define SMC_inw(a, r) readw((a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
-#define SMC_inl(a, r) readl((a) + (r))
-#define SMC_outl(v, a, r) writel(v, (a) + (r))
-#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
-#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
-# else
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-#define SMC_USE_BFIN_DMA 0
-
-
-#define SMC_inw(a, r) readw((a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
-#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
-#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
-# endif
-/* check if the mac in reg is valid */
-#define SMC_GET_MAC_ADDR(addr) \
- do { \
- unsigned int __v; \
- __v = SMC_inw(ioaddr, ADDR0_REG); \
- addr[0] = __v; addr[1] = __v >> 8; \
- __v = SMC_inw(ioaddr, ADDR1_REG); \
- addr[2] = __v; addr[3] = __v >> 8; \
- __v = SMC_inw(ioaddr, ADDR2_REG); \
- addr[4] = __v; addr[5] = __v >> 8; \
- if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
- random_ether_addr(addr); \
- } \
- } while (0)
#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
/* We can only do 16-bit reads and writes in the static memory space. */
#elif defined(CONFIG_SA1100_ASSABET)
-#include <asm/arch/neponset.h>
+#include <mach/neponset.h>
/* We can only do 8-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT 1
#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
#define SMC_IRQ_FLAGS (-1) /* from resource */
-#elif defined(CONFIG_MACH_LOGICPD_PXA270)
+#elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
+ defined(CONFIG_MACH_NOMADIK_8815NHK)
#define SMC_CAN_USE_8BIT 0
#define SMC_CAN_USE_16BIT 1
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#elif defined(CONFIG_ARCH_INNOKOM) || \
- defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_ARCH_PXA_IDP) || \
defined(CONFIG_ARCH_RAMSES) || \
defined(CONFIG_ARCH_PCM027)
}
}
-#elif defined(CONFIG_MACH_ZYLONITE)
-
-#define SMC_CAN_USE_8BIT 1
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-#define SMC_USE_PXA_DMA 1
-#define SMC_inb(a, r) readb((a) + (r))
-#define SMC_inw(a, r) readw((a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-#define SMC_outb(v, a, r) writeb(v, (a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
-#define SMC_IRQ_FLAGS (-1) /* from resource */
-
-#elif defined(CONFIG_ARCH_OMAP)
-
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-
-#define SMC_inw(a, r) readw((a) + (r))
-#define SMC_outw(v, a, r) writew(v, (a) + (r))
-#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
-#define SMC_IRQ_FLAGS (-1) /* from resource */
-
#elif defined(CONFIG_SH_SH4202_MICRODEV)
#define SMC_CAN_USE_8BIT 0
#define SMC_IRQ_FLAGS (0)
-#elif defined(CONFIG_ISA)
-
-#define SMC_CAN_USE_8BIT 1
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-
-#define SMC_inb(a, r) inb((a) + (r))
-#define SMC_inw(a, r) inw((a) + (r))
-#define SMC_outb(v, a, r) outb(v, (a) + (r))
-#define SMC_outw(v, a, r) outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-
-#elif defined(CONFIG_SUPERH)
-
-#ifdef CONFIG_SOLUTION_ENGINE
-#define SMC_IRQ_FLAGS (0)
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-
-#define SMC_inw(a, r) inw((a) + (r))
-#define SMC_outw(v, a, r) outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-
-#else /* BOARDS */
-
-#define SMC_CAN_USE_8BIT 1
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-
-#define SMC_inb(a, r) inb((a) + (r))
-#define SMC_inw(a, r) inw((a) + (r))
-#define SMC_outb(v, a, r) outb(v, (a) + (r))
-#define SMC_outw(v, a, r) outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
-
-#endif /* BOARDS */
-
#elif defined(CONFIG_M32R)
#define SMC_CAN_USE_8BIT 0
#define RPC_LSA_DEFAULT RPC_LED_TX_RX
#define RPC_LSB_DEFAULT RPC_LED_100_10
-#elif defined(CONFIG_MACH_LPD79520) \
- || defined(CONFIG_MACH_LPD7A400) \
- || defined(CONFIG_MACH_LPD7A404)
+#elif defined(CONFIG_MACH_LPD79520) || \
+ defined(CONFIG_MACH_LPD7A400) || \
+ defined(CONFIG_MACH_LPD7A404)
/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
* way that the CPU handles chip selects and the way that the SMC chip
* IOBARRIER on entry to their ISR.
*/
-#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
+#include <mach/constants.h> /* IOBARRIER_VIRT */
#define SMC_CAN_USE_8BIT 0
#define SMC_CAN_USE_16BIT 1
#define RPC_LSA_DEFAULT RPC_LED_TX_RX
#define RPC_LSB_DEFAULT RPC_LED_100_10
-#elif defined(CONFIG_SOC_AU1X00)
-
-#include <au1xxx.h>
-
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_IO_SHIFT 0
-#define SMC_NOWAIT 1
-
-#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
-#define SMC_insw(a, r, p, l) \
- do { \
- unsigned long _a = (unsigned long)((a) + (r)); \
- int _l = (l); \
- u16 *_p = (u16 *)(p); \
- while (_l-- > 0) \
- *_p++ = au_readw(_a); \
- } while(0)
-#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
-#define SMC_outsw(a, r, p, l) \
- do { \
- unsigned long _a = (unsigned long)((a) + (r)); \
- int _l = (l); \
- const u16 *_p = (const u16 *)(p); \
- while (_l-- > 0) \
- au_writew(*_p++ , _a); \
- } while(0)
-
-#define SMC_IRQ_FLAGS (0)
-
#elif defined(CONFIG_ARCH_VERSATILE)
#define SMC_CAN_USE_8BIT 1
* MN10300/AM33 configuration
*/
-#include <asm/unit/smc91111.h>
+#include <unit/smc91111.h>
+
+#elif defined(CONFIG_ARCH_MSM)
+
+#define SMC_CAN_USE_8BIT 0
+#define SMC_CAN_USE_16BIT 1
+#define SMC_CAN_USE_32BIT 0
+#define SMC_NOWAIT 1
+
+#define SMC_inw(a, r) readw((a) + (r))
+#define SMC_outw(v, a, r) writew(v, (a) + (r))
+#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
+#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
+
+#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
+
+#elif defined(CONFIG_COLDFIRE)
+
+#define SMC_CAN_USE_8BIT 0
+#define SMC_CAN_USE_16BIT 1
+#define SMC_CAN_USE_32BIT 0
+#define SMC_NOWAIT 1
+
+static inline void mcf_insw(void *a, unsigned char *p, int l)
+{
+ u16 *wp = (u16 *) p;
+ while (l-- > 0)
+ *wp++ = readw(a);
+}
+
+static inline void mcf_outsw(void *a, unsigned char *p, int l)
+{
+ u16 *wp = (u16 *) p;
+ while (l-- > 0)
+ writew(*wp++, a);
+}
+
+#define SMC_inw(a, r) _swapw(readw((a) + (r)))
+#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
+#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
+#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
+
+#define SMC_IRQ_FLAGS (IRQF_DISABLED)
#else
#define SMC_CAN_USE_32BIT 1
#define SMC_NOWAIT 1
+#define SMC_IO_SHIFT (lp->io_shift)
+
#define SMC_inb(a, r) readb((a) + (r))
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_inl(a, r) readl((a) + (r))
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_outl(v, a, r) writel(v, (a) + (r))
+#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
+#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
spinlock_t lock;
-#ifdef SMC_USE_PXA_DMA
+#ifdef CONFIG_ARCH_PXA
/* DMA needs the physical address of the chip */
u_long physaddr;
struct device *device;
#endif
void __iomem *base;
void __iomem *datacs;
+
+ /* the low address lines on some platforms aren't connected... */
+ int io_shift;
+
+ struct smc91x_platdata cfg;
};
+#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
+#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
+#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
-#ifdef SMC_USE_PXA_DMA
+#ifdef CONFIG_ARCH_PXA
/*
* Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
* always happening in irq context so no need to worry about races. TX is
* as RX which can overrun memory and lose packets.
*/
#include <linux/dma-mapping.h>
-#include <asm/dma.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/dma.h>
#ifdef SMC_insl
#undef SMC_insl
{
DCSR(dma) = 0;
}
-#endif /* SMC_USE_PXA_DMA */
+#endif /* CONFIG_ARCH_PXA */
/*
#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
-#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
-#define RPC_LED_RES (0x01) // LED = Reserved
-#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
-#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
-#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
-#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
-#define RPC_LED_TX (0x06) // LED = TX packet occurred
-#define RPC_LED_RX (0x07) // LED = RX packet occurred
#ifndef RPC_LSA_DEFAULT
#define RPC_LSA_DEFAULT RPC_LED_100
#define RPC_LSB_DEFAULT RPC_LED_FD
#endif
-#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
+#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
/* Bank 0 0x0C is reserved */
*
* Enforce it on any 32-bit capable setup for now.
*/
-#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
+#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
#define SMC_GET_PN(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
#define SMC_SET_PN(lp, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(lp)) \
SMC_outb(x, ioaddr, PN_REG(lp)); \
else \
SMC_outw(x, ioaddr, PN_REG(lp)); \
} while (0)
#define SMC_GET_AR(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
#define SMC_GET_TXFIFO(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
#define SMC_GET_RXFIFO(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
#define SMC_GET_INT(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
#define SMC_ACK_INT(lp, x) \
do { \
- if (SMC_CAN_USE_8BIT) \
+ if (SMC_8BIT(lp)) \
SMC_outb(x, ioaddr, INT_REG(lp)); \
else { \
unsigned long __flags; \
} while (0)
#define SMC_GET_INT_MASK(lp) \
- (SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG(lp))) \
+ (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
#define SMC_SET_INT_MASK(lp, x) \
do { \
- if (SMC_CAN_USE_8BIT) \
+ if (SMC_8BIT(lp)) \
SMC_outb(x, ioaddr, IM_REG(lp)); \
else \
SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
#define SMC_SELECT_BANK(lp, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
else \
SMC_outw(x, ioaddr, BANK_SELECT); \
#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
+#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
+
+#define SMC_SET_GP(lp, x) \
+ do { \
+ if (SMC_MUST_ALIGN_WRITE(lp)) \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
+ else \
+ SMC_outw(x, ioaddr, GP_REG(lp)); \
+ } while (0)
+
#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
#define SMC_SET_PTR(lp, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
else \
SMC_outw(x, ioaddr, PTR_REG(lp)); \
#define SMC_SET_RPC(lp, x) \
do { \
- if (SMC_MUST_ALIGN_WRITE) \
+ if (SMC_MUST_ALIGN_WRITE(lp)) \
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
else \
SMC_outw(x, ioaddr, RPC_REG(lp)); \
#define SMC_PUT_PKT_HDR(lp, status, length) \
do { \
- if (SMC_CAN_USE_32BIT) \
+ if (SMC_32BIT(lp)) \
SMC_outl((status) | (length)<<16, ioaddr, \
DATA_REG(lp)); \
else { \
#define SMC_GET_PKT_HDR(lp, status, length) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(lp)) { \
unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
(status) = __val & 0xffff; \
(length) = __val >> 16; \
#define SMC_PUSH_DATA(lp, p, l) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(lp)) { \
void *__ptr = (p); \
int __len = (l); \
void __iomem *__ioaddr = ioaddr; \
SMC_outw(*((u16 *)__ptr), ioaddr, \
DATA_REG(lp)); \
} \
- } else if (SMC_CAN_USE_16BIT) \
+ } else if (SMC_16BIT(lp)) \
SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(lp)) \
SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
} while (0)
#define SMC_PULL_DATA(lp, p, l) \
do { \
- if (SMC_CAN_USE_32BIT) { \
+ if (SMC_32BIT(lp)) { \
void *__ptr = (p); \
int __len = (l); \
void __iomem *__ioaddr = ioaddr; \
__ioaddr = lp->datacs; \
__len += 2; \
SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
- } else if (SMC_CAN_USE_16BIT) \
+ } else if (SMC_16BIT(lp)) \
SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
- else if (SMC_CAN_USE_8BIT) \
+ else if (SMC_8BIT(lp)) \
SMC_insb(ioaddr, DATA_REG(lp), p, l); \
} while (0)
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff