*/
/*
- * TODO
- * - coalescing setting?
- * - vlan support
- *
* TOTEST
- * - variable ring size
* - speed setting
- * - power management
- * - netpoll
+ * - suspend/resume
*/
#include <linux/config.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/netdevice.h>
+#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/pci.h>
#include <linux/tcp.h>
#include <linux/in.h>
#include <linux/delay.h>
+#include <linux/workqueue.h>
+#include <linux/if_vlan.h>
+#include <linux/prefetch.h>
+#include <linux/mii.h>
#include <asm/irq.h>
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#define SKY2_VLAN_TAG_USED 1
+#endif
+
#include "sky2.h"
#define DRV_NAME "sky2"
-#define DRV_VERSION "0.5"
+#define DRV_VERSION "0.10"
#define PFX DRV_NAME " "
/*
* a receive requires one (or two if using 64 bit dma).
*/
-#ifdef CONFIG_SKY2_EC_A1
#define is_ec_a1(hw) \
- ((hw)->chip_id == CHIP_ID_YUKON_EC && \
- (hw)->chip_rev == CHIP_REV_YU_EC_A1)
-#else
-#define is_ec_a1(hw) 0
-#endif
+ unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
+ (hw)->chip_rev == CHIP_REV_YU_EC_A1)
-#define RX_LE_SIZE 256
+#define RX_LE_SIZE 512
#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
-#define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
-#define RX_DEF_PENDING 128
-#define RX_COPY_THRESHOLD 256
+#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
+#define RX_DEF_PENDING RX_MAX_PENDING
#define TX_RING_SIZE 512
#define TX_DEF_PENDING (TX_RING_SIZE - 1)
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
+static int copybreak __read_mostly = 256;
+module_param(copybreak, int, 0);
+MODULE_PARM_DESC(copybreak, "Receive copy threshold");
+
static const struct pci_device_id sky2_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
{ 0 }
};
static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
-static const char *yukon_name[] = {
- [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
- [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
- [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
-
- [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
- [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
+/* This driver supports yukon2 chipset only */
+static const char *yukon2_name[] = {
+ "XL", /* 0xb3 */
+ "EC Ultra", /* 0xb4 */
+ "UNKNOWN", /* 0xb5 */
+ "EC", /* 0xb6 */
+ "FE", /* 0xb7 */
};
-
/* Access to external PHY */
-static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
+static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
{
int i;
for (i = 0; i < PHY_RETRIES; i++) {
if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
- return;
+ return 0;
udelay(1);
}
+
printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
+ return -ETIMEDOUT;
}
-static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
+static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
{
int i;
| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
for (i = 0; i < PHY_RETRIES; i++) {
- if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
- goto ready;
+ if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
+ *val = gma_read16(hw, port, GM_SMI_DATA);
+ return 0;
+ }
+
udelay(1);
}
- printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
-ready:
- return gma_read16(hw, port, GM_SMI_DATA);
+ return -ETIMEDOUT;
+}
+
+static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
+{
+ u16 v;
+
+ if (__gm_phy_read(hw, port, reg, &v) != 0)
+ printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
+ return v;
+}
+
+static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
+{
+ u16 power_control;
+ u32 reg1;
+ int vaux;
+ int ret = 0;
+
+ pr_debug("sky2_set_power_state %d\n", state);
+ sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+
+ pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
+ vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
+ (power_control & PCI_PM_CAP_PME_D3cold);
+
+ pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
+
+ power_control |= PCI_PM_CTRL_PME_STATUS;
+ power_control &= ~(PCI_PM_CTRL_STATE_MASK);
+
+ switch (state) {
+ case PCI_D0:
+ /* switch power to VCC (WA for VAUX problem) */
+ sky2_write8(hw, B0_POWER_CTRL,
+ PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
+
+ /* disable Core Clock Division, */
+ sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
+
+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
+ /* enable bits are inverted */
+ sky2_write8(hw, B2_Y2_CLK_GATE,
+ Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
+ else
+ sky2_write8(hw, B2_Y2_CLK_GATE, 0);
+
+ /* Turn off phy power saving */
+ pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
+ reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
+
+ /* looks like this XL is back asswards .. */
+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
+ reg1 |= PCI_Y2_PHY1_COMA;
+ if (hw->ports > 1)
+ reg1 |= PCI_Y2_PHY2_COMA;
+ }
+ pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
+ break;
+
+ case PCI_D3hot:
+ case PCI_D3cold:
+ /* Turn on phy power saving */
+ pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
+ reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
+ else
+ reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
+ pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
+
+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
+ sky2_write8(hw, B2_Y2_CLK_GATE, 0);
+ else
+ /* enable bits are inverted */
+ sky2_write8(hw, B2_Y2_CLK_GATE,
+ Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
+
+ /* switch power to VAUX */
+ if (vaux && state != PCI_D3cold)
+ sky2_write8(hw, B0_POWER_CTRL,
+ (PC_VAUX_ENA | PC_VCC_ENA |
+ PC_VAUX_ON | PC_VCC_OFF));
+ break;
+ default:
+ printk(KERN_ERR PFX "Unknown power state %d\n", state);
+ ret = -1;
+ }
+
+ pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
+ sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+ return ret;
}
static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
if (ledover)
gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
- /* Enable phy interrupt on autonegotiation complete (or link up) */
+ /* Enable phy interrupt on auto-negotiation complete (or link up) */
if (sky2->autoneg == AUTONEG_ENABLE)
gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
else
int i;
const u8 *addr = hw->dev[port]->dev_addr;
- sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
- sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
+ sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
+ sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
- spin_lock_bh(&hw->phy_lock);
+ down(&sky2->phy_sema);
sky2_phy_init(hw, port);
- spin_unlock_bh(&hw->phy_lock);
+ up(&sky2->phy_sema);
/* MIB clear */
reg = gma_read16(hw, port, GM_PHY_ADDR);
/* Configure Rx MAC FIFO */
sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
- GMF_OPER_ON | GMF_RX_F_FL_ON);
+ GMF_RX_CTRL_DEF);
- /* Flush Rx MAC FIFO on any flowcontrol or error */
- reg = GMR_FS_ANY_ERR;
- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
- reg = 0; /* WA Dev #4115 */
+ /* Flush Rx MAC FIFO on any flow control or error */
+ sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
- sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
/* Set threshold to 0xa (64 bytes)
* ASF disabled so no need to do WA dev #4.30
*/
/* Configure Tx MAC FIFO */
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
+
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+ sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
+ sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
+ if (hw->dev[port]->mtu > ETH_DATA_LEN) {
+ /* set Tx GMAC FIFO Almost Empty Threshold */
+ sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
+ /* Disable Store & Forward mode for TX */
+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
+ }
+ }
+
}
static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
}
/* Setup Bus Memory Interface */
-static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
+static void sky2_qset(struct sky2_hw *hw, u16 q)
{
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
- sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
+ sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
}
/* Setup prefetch unit registers. This is the interface between
* hardware and driver list elements
*/
-static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
+static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
u64 addr, u32 last)
{
sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
}
/*
- * This is a workaround code taken from syskonnect sk98lin driver
+ * This is a workaround code taken from SysKonnect sk98lin driver
* to deal with chip bug on Yukon EC rev 0 in the wraparound case.
*/
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
setnew:
sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
}
- *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
+ *last = idx;
}
return le;
}
+/* Return high part of DMA address (could be 32 or 64 bit) */
+static inline u32 high32(dma_addr_t a)
+{
+ return (a >> 16) >> 16;
+}
+
/* Build description to hardware about buffer */
-static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
+static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
{
struct sky2_rx_le *le;
- u32 hi = (re->mapaddr >> 16) >> 16;
+ u32 hi = high32(map);
+ u16 len = sky2->rx_bufsize;
- re->idx = sky2->rx_put;
if (sky2->rx_addr64 != hi) {
le = sky2_next_rx(sky2);
le->addr = cpu_to_le32(hi);
le->ctrl = 0;
le->opcode = OP_ADDR64 | HW_OWNER;
- sky2->rx_addr64 = hi;
+ sky2->rx_addr64 = high32(map + len);
}
le = sky2_next_rx(sky2);
- le->addr = cpu_to_le32((u32) re->mapaddr);
- le->length = cpu_to_le16(re->maplen);
+ le->addr = cpu_to_le32((u32) map);
+ le->length = cpu_to_le16(len);
le->ctrl = 0;
le->opcode = OP_PACKET | HW_OWNER;
}
-/* Tell receiver about new buffers. */
-static inline void rx_set_put(struct net_device *dev)
-{
- struct sky2_port *sky2 = netdev_priv(dev);
-
- if (sky2->rx_last_put != sky2->rx_put)
- sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
- &sky2->rx_last_put, RX_LE_SIZE);
-}
/* Tell chip where to start receive checksum.
* Actually has two checksums, but set both same to avoid possible byte
sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
}
-/* Cleanout receive buffer area, assumes receiver hardware stopped */
+/* Clean out receive buffer area, assumes receiver hardware stopped */
static void sky2_rx_clean(struct sky2_port *sky2)
{
unsigned i;
if (re->skb) {
pci_unmap_single(sky2->hw->pdev,
- re->mapaddr, re->maplen,
+ re->mapaddr, sky2->rx_bufsize,
PCI_DMA_FROMDEVICE);
kfree_skb(re->skb);
re->skb = NULL;
}
}
-#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
-static inline unsigned rx_size(const struct sky2_port *sky2)
+/* Basic MII support */
+static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
- return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
+ struct mii_ioctl_data *data = if_mii(ifr);
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ int err = -EOPNOTSUPP;
+
+ if (!netif_running(dev))
+ return -ENODEV; /* Phy still in reset */
+
+ switch(cmd) {
+ case SIOCGMIIPHY:
+ data->phy_id = PHY_ADDR_MARV;
+
+ /* fallthru */
+ case SIOCGMIIREG: {
+ u16 val = 0;
+
+ down(&sky2->phy_sema);
+ err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
+ up(&sky2->phy_sema);
+
+ data->val_out = val;
+ break;
+ }
+
+ case SIOCSMIIREG:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ down(&sky2->phy_sema);
+ err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
+ data->val_in);
+ up(&sky2->phy_sema);
+ break;
+ }
+ return err;
}
+#ifdef SKY2_VLAN_TAG_USED
+static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+{
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ u16 port = sky2->port;
+
+ spin_lock(&sky2->tx_lock);
+
+ sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
+ sky2->vlgrp = grp;
+
+ spin_unlock(&sky2->tx_lock);
+}
+
+static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
+{
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ u16 port = sky2->port;
+
+ spin_lock(&sky2->tx_lock);
+
+ sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
+ if (sky2->vlgrp)
+ sky2->vlgrp->vlan_devices[vid] = NULL;
+
+ spin_unlock(&sky2->tx_lock);
+}
+#endif
+
/*
* Allocate and setup receiver buffer pool.
* In case of 64 bit dma, there are 2X as many list elements
static int sky2_rx_start(struct sky2_port *sky2)
{
struct sky2_hw *hw = sky2->hw;
- unsigned size = rx_size(sky2);
unsigned rxq = rxqaddr[sky2->port];
int i;
sky2->rx_put = sky2->rx_next = 0;
- sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
+ sky2_qset(hw, rxq);
sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
rx_set_checksum(sky2);
for (i = 0; i < sky2->rx_pending; i++) {
struct ring_info *re = sky2->rx_ring + i;
- re->skb = dev_alloc_skb(size);
+ re->skb = dev_alloc_skb(sky2->rx_bufsize);
if (!re->skb)
goto nomem;
re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
- size, PCI_DMA_FROMDEVICE);
- re->maplen = size;
- sky2_rx_add(sky2, re);
+ sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
+ sky2_rx_add(sky2, re->mapaddr);
}
/* Tell chip about available buffers */
if (!sky2->tx_le)
goto err_out;
- sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
+ sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
GFP_KERNEL);
if (!sky2->tx_ring)
goto err_out;
sky2->tx_prod = sky2->tx_cons = 0;
- memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
&sky2->rx_le_map);
goto err_out;
memset(sky2->rx_le, 0, RX_LE_BYTES);
- sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
+ sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
GFP_KERNEL);
if (!sky2->rx_ring)
goto err_out;
sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
RB_RST_SET);
- sky2_qset(hw, txqaddr[port], 0x600);
+ sky2_qset(hw, txqaddr[port]);
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U)
+ sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
+
+
sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
TX_RING_SIZE - 1);
/* Modular subtraction in ring */
static inline int tx_dist(unsigned tail, unsigned head)
{
- return (head >= tail ? head : head + TX_RING_SIZE) - tail;
+ return (head - tail) % TX_RING_SIZE;
}
/* Number of list elements available for next tx */
if (skb_shinfo(skb)->tso_size)
++count;
- if (skb->ip_summed)
+ if (skb->ip_summed == CHECKSUM_HW)
++count;
return count;
* A single packet can generate multiple list elements, and
* the number of ring elements will probably be less than the number
* of list elements used.
+ *
+ * No BH disabling for tx_lock here (like tg3)
*/
static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
{
struct sky2_port *sky2 = netdev_priv(dev);
struct sky2_hw *hw = sky2->hw;
- struct sky2_tx_le *le;
- struct ring_info *re;
- unsigned long flags;
+ struct sky2_tx_le *le = NULL;
+ struct tx_ring_info *re;
unsigned i, len;
dma_addr_t mapping;
u32 addr64;
u16 mss;
u8 ctrl;
- local_irq_save(flags);
- if (!spin_trylock(&sky2->tx_lock)) {
- local_irq_restore(flags);
+ if (!spin_trylock(&sky2->tx_lock))
return NETDEV_TX_LOCKED;
- }
if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
- netif_stop_queue(dev);
- spin_unlock_irqrestore(&sky2->tx_lock, flags);
+ /* There is a known but harmless race with lockless tx
+ * and netif_stop_queue.
+ */
+ if (!netif_queue_stopped(dev)) {
+ netif_stop_queue(dev);
+ printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
+ dev->name);
+ }
+ spin_unlock(&sky2->tx_lock);
- printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
- dev->name);
return NETDEV_TX_BUSY;
}
len = skb_headlen(skb);
mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
- addr64 = (mapping >> 16) >> 16;
+ addr64 = high32(mapping);
re = sky2->tx_ring + sky2->tx_prod;
- /* Send high bits if changed */
- if (addr64 != sky2->tx_addr64) {
+ /* Send high bits if changed or crosses boundary */
+ if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
le = get_tx_le(sky2);
le->tx.addr = cpu_to_le32(addr64);
le->ctrl = 0;
le->opcode = OP_ADDR64 | HW_OWNER;
- sky2->tx_addr64 = addr64;
+ sky2->tx_addr64 = high32(mapping + len);
}
/* Check for TCP Segmentation Offload */
sky2->tx_last_mss = mss;
}
- /* Handle TCP checksum offload */
ctrl = 0;
+#ifdef SKY2_VLAN_TAG_USED
+ /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
+ if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
+ if (!le) {
+ le = get_tx_le(sky2);
+ le->tx.addr = 0;
+ le->opcode = OP_VLAN|HW_OWNER;
+ le->ctrl = 0;
+ } else
+ le->opcode |= OP_VLAN;
+ le->length = cpu_to_be16(vlan_tx_tag_get(skb));
+ ctrl |= INS_VLAN;
+ }
+#endif
+
+ /* Handle TCP checksum offload */
if (skb->ip_summed == CHECKSUM_HW) {
u16 hdr = skb->h.raw - skb->data;
u16 offset = hdr + skb->csum;
/* Record the transmit mapping info */
re->skb = skb;
- re->mapaddr = mapping;
- re->maplen = len;
+ pci_unmap_addr_set(re, mapaddr, mapping);
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
- struct ring_info *fre;
+ struct tx_ring_info *fre;
mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
frag->size, PCI_DMA_TODEVICE);
fre = sky2->tx_ring
+ ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
- fre->skb = NULL;
- fre->mapaddr = mapping;
- fre->maplen = frag->size;
+ pci_unmap_addr_set(fre, mapaddr, mapping);
}
+
re->idx = sky2->tx_prod;
le->ctrl |= EOP;
- sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
+ sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
&sky2->tx_last_put, TX_RING_SIZE);
- if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
+ if (tx_avail(sky2) <= MAX_SKB_TX_LE)
netif_stop_queue(dev);
out_unlock:
mmiowb();
- spin_unlock_irqrestore(&sky2->tx_lock, flags);
+ spin_unlock(&sky2->tx_lock);
dev->trans_start = jiffies;
return NETDEV_TX_OK;
* Free ring elements from starting at tx_cons until "done"
*
* NB: the hardware will tell us about partial completion of multi-part
- * buffers; these are defered until completion.
+ * buffers; these are deferred until completion.
*/
static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
{
struct net_device *dev = sky2->netdev;
+ struct pci_dev *pdev = sky2->hw->pdev;
+ u16 nxt, put;
unsigned i;
+ BUG_ON(done >= TX_RING_SIZE);
+
if (unlikely(netif_msg_tx_done(sky2)))
- printk(KERN_DEBUG "%s: tx done, upto %u\n",
+ printk(KERN_DEBUG "%s: tx done, up to %u\n",
dev->name, done);
- spin_lock(&sky2->tx_lock);
+ for (put = sky2->tx_cons; put != done; put = nxt) {
+ struct tx_ring_info *re = sky2->tx_ring + put;
+ struct sk_buff *skb = re->skb;
- while (sky2->tx_cons != done) {
- struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
- struct sk_buff *skb;
+ nxt = re->idx;
+ BUG_ON(nxt >= TX_RING_SIZE);
+ prefetch(sky2->tx_ring + nxt);
/* Check for partial status */
- if (tx_dist(sky2->tx_cons, done)
- < tx_dist(sky2->tx_cons, re->idx))
- goto out;
+ if (tx_dist(put, done) < tx_dist(put, nxt))
+ break;
skb = re->skb;
- pci_unmap_single(sky2->hw->pdev,
- re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
+ pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
+ skb_headlen(skb), PCI_DMA_TODEVICE);
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- struct ring_info *fre;
- fre =
- sky2->tx_ring + (sky2->tx_cons + i +
- 1) % TX_RING_SIZE;
- pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
- fre->maplen, PCI_DMA_TODEVICE);
+ struct tx_ring_info *fre;
+ fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
+ pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
+ skb_shinfo(skb)->frags[i].size,
+ PCI_DMA_TODEVICE);
}
dev_kfree_skb_any(skb);
-
- sky2->tx_cons = re->idx;
}
-out:
+ spin_lock(&sky2->tx_lock);
+ sky2->tx_cons = put;
if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
netif_wake_queue(dev);
spin_unlock(&sky2->tx_lock);
}
/* Cleanup all untransmitted buffers, assume transmitter not running */
-static inline void sky2_tx_clean(struct sky2_port *sky2)
+static void sky2_tx_clean(struct sky2_port *sky2)
{
sky2_tx_complete(sky2, sky2->tx_prod);
}
if (netif_msg_ifdown(sky2))
printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
+ /* Stop more packets from being queued */
netif_stop_queue(dev);
+ /* Disable port IRQ */
+ local_irq_disable();
+ hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
+ sky2_write32(hw, B0_IMSK, hw->intr_mask);
+ local_irq_enable();
+
+ flush_scheduled_work();
+
sky2_phy_reset(hw, port);
/* Stop transmitter */
sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
- /* turn off led's */
+ /* turn off LED's */
sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
+ synchronize_irq(hw->pdev->irq);
+
sky2_tx_clean(sky2);
sky2_rx_clean(sky2);
unsigned port = sky2->port;
u16 reg;
- /* disable Rx GMAC FIFO flush mode */
- sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
-
/* Enable Transmit FIFO Underrun */
sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
if (netif_msg_link(sky2))
printk(KERN_INFO PFX
- "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
+ "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
sky2->netdev->name, sky2->speed,
sky2->duplex == DUPLEX_FULL ? "full" : "half",
(sky2->tx_pause && sky2->rx_pause) ? "both" :
}
/*
- * Interrrupt from PHY are handled in tasklet (soft irq)
+ * Interrupt from PHY are handled outside of interrupt context
* because accessing phy registers requires spin wait which might
* cause excess interrupt latency.
*/
-static void sky2_phy_task(unsigned long data)
+static void sky2_phy_task(void *arg)
{
- struct sky2_port *sky2 = (struct sky2_port *)data;
+ struct sky2_port *sky2 = arg;
struct sky2_hw *hw = sky2->hw;
u16 istatus, phystat;
- spin_lock(&hw->phy_lock);
+ down(&sky2->phy_sema);
istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
sky2_link_down(sky2);
}
out:
- spin_unlock(&hw->phy_lock);
+ up(&sky2->phy_sema);
local_irq_disable();
hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
static void sky2_tx_timeout(struct net_device *dev)
{
struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ unsigned txq = txqaddr[sky2->port];
if (netif_msg_timer(sky2))
printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
- sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
- sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
+ netif_stop_queue(dev);
+
+ sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
+ sky2_read32(hw, Q_ADDR(txq, Q_CSR));
+
+ sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
sky2_tx_clean(sky2);
+
+ sky2_qset(hw, txq);
+ sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
+
+ netif_wake_queue(dev);
+}
+
+
+#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
+/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
+static inline unsigned sky2_buf_size(int mtu)
+{
+ return roundup(mtu + ETH_HLEN + 4, 8);
}
static int sky2_change_mtu(struct net_device *dev, int new_mtu)
if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
return -EINVAL;
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+
if (!netif_running(dev)) {
dev->mtu = new_mtu;
return 0;
}
- local_irq_disable();
sky2_write32(hw, B0_IMSK, 0);
+ dev->trans_start = jiffies; /* prevent tx timeout */
+ netif_stop_queue(dev);
+ netif_poll_disable(hw->dev[0]);
+
ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
sky2_rx_stop(sky2);
sky2_rx_clean(sky2);
dev->mtu = new_mtu;
+ sky2->rx_bufsize = sky2_buf_size(new_mtu);
mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
err = sky2_rx_start(sky2);
gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
+ netif_poll_disable(hw->dev[0]);
+ netif_wake_queue(dev);
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- sky2_read32(hw, B0_IMSK);
- local_irq_enable();
+
return err;
}
/*
* Receive one packet.
* For small packets or errors, just reuse existing skb.
- * For larger pakects, get new buffer.
+ * For larger packets, get new buffer.
*/
static struct sk_buff *sky2_receive(struct sky2_port *sky2,
u16 length, u32 status)
{
struct ring_info *re = sky2->rx_ring + sky2->rx_next;
struct sk_buff *skb = NULL;
- struct net_device *dev;
- const unsigned int bufsize = rx_size(sky2);
if (unlikely(netif_msg_rx_status(sky2)))
printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
sky2->netdev->name, sky2->rx_next, status, length);
sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
+ prefetch(sky2->rx_ring + sky2->rx_next);
- if (!(status & GMR_FS_RX_OK)
- || (status & GMR_FS_ANY_ERR)
- || (length << 16) != (status & GMR_FS_LEN)
- || length > bufsize)
+ if (status & GMR_FS_ANY_ERR)
goto error;
- if (length < RX_COPY_THRESHOLD) {
+ if (!(status & GMR_FS_RX_OK))
+ goto resubmit;
+
+ if (length < copybreak) {
skb = alloc_skb(length + 2, GFP_ATOMIC);
if (!skb)
goto resubmit;
} else {
struct sk_buff *nskb;
- nskb = dev_alloc_skb(bufsize);
+ nskb = dev_alloc_skb(sky2->rx_bufsize);
if (!nskb)
goto resubmit;
skb = re->skb;
re->skb = nskb;
pci_unmap_single(sky2->hw->pdev, re->mapaddr,
- re->maplen, PCI_DMA_FROMDEVICE);
+ sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
prefetch(skb->data);
re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
- bufsize, PCI_DMA_FROMDEVICE);
- re->maplen = bufsize;
+ sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
}
skb_put(skb, length);
- dev = sky2->netdev;
- skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
- dev->last_rx = jiffies;
-
resubmit:
re->skb->ip_summed = CHECKSUM_NONE;
- sky2_rx_add(sky2, re);
+ sky2_rx_add(sky2, re->mapaddr);
+
+ /* Tell receiver about new buffers. */
+ sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
+ &sky2->rx_last_put, RX_LE_SIZE);
return skb;
error:
- if (status & GMR_FS_GOOD_FC)
- goto resubmit;
-
if (netif_msg_rx_err(sky2))
printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
sky2->netdev->name, status, length);
goto resubmit;
}
-/* Transmit ring index in reported status block is encoded as:
- *
- * | TXS2 | TXA2 | TXS1 | TXA1
+/*
+ * Check for transmit complete
*/
-static inline u16 tx_index(u8 port, u32 status, u16 len)
+#define TX_NO_STATUS 0xffff
+
+static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
{
- if (port == 0)
- return status & 0xfff;
- else
- return ((status >> 24) & 0xff) | (len & 0xf) << 8;
+ if (last != TX_NO_STATUS) {
+ struct net_device *dev = hw->dev[port];
+ if (dev && netif_running(dev)) {
+ struct sky2_port *sky2 = netdev_priv(dev);
+ sky2_tx_complete(sky2, last);
+ }
+ }
}
/*
unsigned int to_do = min(dev0->quota, *budget);
unsigned int work_done = 0;
u16 hwidx;
+ u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
hwidx = sky2_read16(hw, STAT_PUT_IDX);
BUG_ON(hwidx >= STATUS_RING_SIZE);
- rmb();
- while (hw->st_idx != hwidx && work_done < to_do) {
- struct sky2_status_le *le = hw->st_le + hw->st_idx;
+ rmb();
+
+ while (hwidx != hw->st_idx) {
+ struct sky2_status_le *le = hw->st_le + hw->st_idx;
+ struct net_device *dev;
struct sky2_port *sky2;
struct sk_buff *skb;
u32 status;
u16 length;
+ u8 op;
+
+ le = hw->st_le + hw->st_idx;
+ hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
+ prefetch(hw->st_le + hw->st_idx);
- BUG_ON(le->link >= hw->ports);
- sky2 = netdev_priv(hw->dev[le->link]);
+ BUG_ON(le->link >= 2);
+ dev = hw->dev[le->link];
+ if (dev == NULL || !netif_running(dev))
+ continue;
+
+ sky2 = netdev_priv(dev);
status = le32_to_cpu(le->status);
length = le16_to_cpu(le->length);
+ op = le->opcode & ~HW_OWNER;
+ le->opcode = 0;
- switch (le->opcode & ~HW_OWNER) {
+ switch (op) {
case OP_RXSTAT:
skb = sky2_receive(sky2, length, status);
- if (likely(skb)) {
+ if (!skb)
+ break;
+
+ skb->dev = dev;
+ skb->protocol = eth_type_trans(skb, dev);
+ dev->last_rx = jiffies;
+
+#ifdef SKY2_VLAN_TAG_USED
+ if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
+ vlan_hwaccel_receive_skb(skb,
+ sky2->vlgrp,
+ be16_to_cpu(sky2->rx_tag));
+ } else
+#endif
netif_receive_skb(skb);
- ++work_done;
- }
+
+ if (++work_done >= to_do)
+ goto exit_loop;
break;
+#ifdef SKY2_VLAN_TAG_USED
+ case OP_RXVLAN:
+ sky2->rx_tag = length;
+ break;
+
+ case OP_RXCHKSVLAN:
+ sky2->rx_tag = length;
+ /* fall through */
+#endif
case OP_RXCHKS:
skb = sky2->rx_ring[sky2->rx_next].skb;
skb->ip_summed = CHECKSUM_HW;
break;
case OP_TXINDEXLE:
- sky2_tx_complete(sky2,
- tx_index(sky2->port, status, length));
- break;
-
- case OP_RXTIMESTAMP:
+ /* TX index reports status for both ports */
+ tx_done[0] = status & 0xffff;
+ tx_done[1] = ((status >> 24) & 0xff)
+ | (u16)(length & 0xf) << 8;
break;
default:
if (net_ratelimit())
printk(KERN_WARNING PFX
- "unknown status opcode 0x%x\n",
- le->opcode);
+ "unknown status opcode 0x%x\n", op);
break;
}
-
- hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
- if (hw->st_idx == hwidx) {
- hwidx = sky2_read16(hw, STAT_PUT_IDX);
- rmb();
- }
}
+exit_loop:
+ sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
mmiowb();
- if (hw->dev[0])
- rx_set_put(hw->dev[0]);
-
- if (hw->dev[1])
- rx_set_put(hw->dev[1]);
+ sky2_tx_check(hw, 0, tx_done[0]);
+ sky2_tx_check(hw, 1, tx_done[1]);
- *budget -= work_done;
- dev0->quota -= work_done;
- if (work_done < to_do) {
- /*
- * Another chip workaround, need to restart TX timer if status
- * LE was handled. WA_DEV_43_418
- */
+ if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
+ /* need to restart TX timer */
if (is_ec_a1(hw)) {
sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
}
+ netif_rx_complete(dev0);
hw->intr_mask |= Y2_IS_STAT_BMU;
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- sky2_read32(hw, B0_IMSK);
- netif_rx_complete(dev0);
+ mmiowb();
+ return 0;
+ } else {
+ *budget -= work_done;
+ dev0->quota -= work_done;
+ return 1;
}
-
- return work_done >= to_do;
-
}
static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
}
if (status & Y2_IS_PCI_EXP) {
- /* PCI-Express uncorrectable Error occured */
+ /* PCI-Express uncorrectable Error occurred */
u32 pex_err;
pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- tasklet_schedule(&sky2->phy_task);
+ schedule_work(&sky2->phy_task);
}
static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
{
struct sky2_hw *hw = dev_id;
+ struct net_device *dev0 = hw->dev[0];
u32 status;
status = sky2_read32(hw, B0_Y2_SP_ISRC2);
sky2_hw_intr(hw);
/* Do NAPI for Rx and Tx status */
- if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
- sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
-
+ if (status & Y2_IS_STAT_BMU) {
hw->intr_mask &= ~Y2_IS_STAT_BMU;
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- __netif_rx_schedule(hw->dev[0]);
+
+ if (likely(__netif_rx_schedule_prep(dev0))) {
+ prefetch(&hw->st_le[hw->st_idx]);
+ __netif_rx_schedule(dev0);
+ }
}
if (status & Y2_IS_IRQ_PHY1)
#endif
/* Chip internal frequency for clock calculations */
-static inline u32 sky2_khz(const struct sky2_hw *hw)
+static inline u32 sky2_mhz(const struct sky2_hw *hw)
{
switch (hw->chip_id) {
case CHIP_ID_YUKON_EC:
- return 125000; /* 125 Mhz */
+ case CHIP_ID_YUKON_EC_U:
+ return 125; /* 125 Mhz */
case CHIP_ID_YUKON_FE:
- return 100000; /* 100 Mhz */
+ return 100; /* 100 Mhz */
default: /* YUKON_XL */
- return 156000; /* 156 Mhz */
+ return 156; /* 156 Mhz */
}
}
-static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
+static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
{
- return sky2_khz(hw) * ms;
+ return sky2_mhz(hw) * us;
}
-static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
+static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
{
- return (sky2_khz(hw) * us) / 1000;
+ return clk / sky2_mhz(hw);
}
+
static int sky2_reset(struct sky2_hw *hw)
{
- u32 ctst, power;
+ u32 ctst;
u16 status;
u8 t8, pmd_type;
int i;
}
hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
- /* switch power to VCC (WA for VAUX problem) */
- sky2_write8(hw, B0_POWER_CTRL,
- PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
-
- /* disable Core Clock Division, */
- sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
-
- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
- /* enable bits are inverted */
- sky2_write8(hw, B2_Y2_CLK_GATE,
- Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
- Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
- Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
- else
- sky2_write8(hw, B2_Y2_CLK_GATE, 0);
-
- /* Turn off phy power saving */
- pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
- power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
-
- /* looks like this xl is back asswards .. */
- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
- power |= PCI_Y2_PHY1_COMA;
- if (hw->ports > 1)
- power |= PCI_Y2_PHY2_COMA;
- }
- pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
+ sky2_set_power_state(hw, PCI_D0);
for (i = 0; i < hw->ports; i++) {
sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
- /* Turn on descriptor polling (every 75us) */
- sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
- sky2_write8(hw, B28_DPT_CTRL, DPT_START);
+ /* Turn off descriptor polling */
+ sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
/* Turn off receive timestamp */
sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
}
- if (is_pciex(hw)) {
- u16 pctrl;
-
- /* change Max. Read Request Size to 2048 bytes */
- pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
- pctrl &= ~PEX_DC_MAX_RRS_MSK;
- pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
-
-
- sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
- pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
- sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
- }
-
sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
- spin_lock_bh(&hw->phy_lock);
for (i = 0; i < hw->ports; i++)
sky2_phy_reset(hw, i);
- spin_unlock_bh(&hw->phy_lock);
memset(hw->st_le, 0, STATUS_LE_BYTES);
hw->st_idx = 0;
/* Set the list last index */
sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
- sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
-
/* These status setup values are copied from SysKonnect's driver */
if (is_ec_a1(hw)) {
/* WA for dev. #4.3 */
/* set Status-FIFO ISR watermark */
sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
-
+ sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
} else {
- sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
-
- /* set Status-FIFO watermark */
- sky2_write8(hw, STAT_FIFO_WM, 0x10);
+ sky2_write16(hw, STAT_TX_IDX_TH, 10);
+ sky2_write8(hw, STAT_FIFO_WM, 16);
/* set Status-FIFO ISR watermark */
if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
- sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
-
- else /* WA 4109 */
- sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
+ sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
+ else
+ sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
- sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
+ sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
+ sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
+ sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
}
/* enable status unit */
return sky2->msg_enable;
}
+static int sky2_nway_reset(struct net_device *dev)
+{
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+
+ if (sky2->autoneg != AUTONEG_ENABLE)
+ return -EINVAL;
+
+ netif_stop_queue(dev);
+
+ down(&sky2->phy_sema);
+ sky2_phy_reset(hw, sky2->port);
+ sky2_phy_init(hw, sky2->port);
+ up(&sky2->phy_sema);
+
+ return 0;
+}
+
static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
{
struct sky2_hw *hw = sky2->hw;
reg = gma_read16(hw, port, GM_RX_CTRL);
reg |= GM_RXCR_UCF_ENA;
- if (dev->flags & IFF_PROMISC) /* promiscious */
+ if (dev->flags & IFF_PROMISC) /* promiscuous */
reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
memset(filter, 0xff, sizeof(filter));
/* Can have one global because blinking is controlled by
* ethtool and that is always under RTNL mutex
*/
-static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
+static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
{
u16 pg;
- spin_lock_bh(&hw->phy_lock);
switch (hw->chip_id) {
case CHIP_ID_YUKON_XL:
pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
PHY_M_LED_MO_RX(MO_LED_OFF));
}
- spin_unlock_bh(&hw->phy_lock);
}
/* blink LED's for finding board */
unsigned port = sky2->port;
u16 ledctrl, ledover = 0;
long ms;
+ int interrupted;
int onoff = 1;
if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
ms = data * 1000;
/* save initial values */
- spin_lock_bh(&hw->phy_lock);
+ down(&sky2->phy_sema);
if (hw->chip_id == CHIP_ID_YUKON_XL) {
u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
}
- spin_unlock_bh(&hw->phy_lock);
- while (ms > 0) {
+ interrupted = 0;
+ while (!interrupted && ms > 0) {
sky2_led(hw, port, onoff);
onoff = !onoff;
- if (msleep_interruptible(250))
- break; /* interrupted */
+ up(&sky2->phy_sema);
+ interrupted = msleep_interruptible(250);
+ down(&sky2->phy_sema);
+
ms -= 250;
}
/* resume regularly scheduled programming */
- spin_lock_bh(&hw->phy_lock);
if (hw->chip_id == CHIP_ID_YUKON_XL) {
u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
}
- spin_unlock_bh(&hw->phy_lock);
+ up(&sky2->phy_sema);
return 0;
}
}
#endif
+static int sky2_get_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *ecmd)
+{
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+
+ if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
+ ecmd->tx_coalesce_usecs = 0;
+ else {
+ u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
+ ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
+ }
+ ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
+
+ if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
+ ecmd->rx_coalesce_usecs = 0;
+ else {
+ u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
+ ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
+ }
+ ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
+
+ if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
+ ecmd->rx_coalesce_usecs_irq = 0;
+ else {
+ u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
+ ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
+ }
+
+ ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
+
+ return 0;
+}
+
+/* Note: this affect both ports */
+static int sky2_set_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *ecmd)
+{
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ const u32 tmin = sky2_clk2us(hw, 1);
+ const u32 tmax = 5000;
+
+ if (ecmd->tx_coalesce_usecs != 0 &&
+ (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
+ return -EINVAL;
+
+ if (ecmd->rx_coalesce_usecs != 0 &&
+ (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
+ return -EINVAL;
+
+ if (ecmd->rx_coalesce_usecs_irq != 0 &&
+ (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
+ return -EINVAL;
+
+ if (ecmd->tx_max_coalesced_frames > 0xffff)
+ return -EINVAL;
+ if (ecmd->rx_max_coalesced_frames > 0xff)
+ return -EINVAL;
+ if (ecmd->rx_max_coalesced_frames_irq > 0xff)
+ return -EINVAL;
+
+ if (ecmd->tx_coalesce_usecs == 0)
+ sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
+ else {
+ sky2_write32(hw, STAT_TX_TIMER_INI,
+ sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
+ sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
+ }
+ sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
+
+ if (ecmd->rx_coalesce_usecs == 0)
+ sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
+ else {
+ sky2_write32(hw, STAT_LEV_TIMER_INI,
+ sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
+ sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
+ }
+ sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
+
+ if (ecmd->rx_coalesce_usecs_irq == 0)
+ sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
+ else {
+ sky2_write32(hw, STAT_TX_TIMER_INI,
+ sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
+ sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
+ }
+ sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
+ return 0;
+}
+
static void sky2_get_ringparam(struct net_device *dev,
struct ethtool_ringparam *ering)
{
.get_drvinfo = sky2_get_drvinfo,
.get_msglevel = sky2_get_msglevel,
.set_msglevel = sky2_set_msglevel,
+ .nway_reset = sky2_nway_reset,
.get_regs_len = sky2_get_regs_len,
.get_regs = sky2_get_regs,
.get_link = ethtool_op_get_link,
.get_rx_csum = sky2_get_rx_csum,
.set_rx_csum = sky2_set_rx_csum,
.get_strings = sky2_get_strings,
+ .get_coalesce = sky2_get_coalesce,
+ .set_coalesce = sky2_set_coalesce,
.get_ringparam = sky2_get_ringparam,
.set_ringparam = sky2_set_ringparam,
.get_pauseparam = sky2_get_pauseparam,
.phys_id = sky2_phys_id,
.get_stats_count = sky2_get_stats_count,
.get_ethtool_stats = sky2_get_ethtool_stats,
+ .get_perm_addr = ethtool_op_get_perm_addr,
};
/* Initialize network device */
SET_MODULE_OWNER(dev);
SET_NETDEV_DEV(dev, &hw->pdev->dev);
+ dev->irq = hw->pdev->irq;
dev->open = sky2_up;
dev->stop = sky2_down;
+ dev->do_ioctl = sky2_ioctl;
dev->hard_start_xmit = sky2_xmit_frame;
dev->get_stats = sky2_get_stats;
dev->set_multicast_list = sky2_set_multicast;
spin_lock_init(&sky2->tx_lock);
/* Auto speed and flow control */
sky2->autoneg = AUTONEG_ENABLE;
- sky2->tx_pause = 0;
+ sky2->tx_pause = 1;
sky2->rx_pause = 1;
sky2->duplex = -1;
sky2->speed = -1;
sky2->advertising = sky2_supported_modes(hw);
- sky2->rx_csum = 1;
- tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
+
+ /* Receive checksum disabled for Yukon XL
+ * because of observed problems with incorrect
+ * values when multiple packets are received in one interrupt
+ */
+ sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
+
+ INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
+ init_MUTEX(&sky2->phy_sema);
sky2->tx_pending = TX_DEF_PENDING;
sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
+ sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
hw->dev[port] = dev;
sky2->port = port;
- dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
+ dev->features |= NETIF_F_LLTX;
+ if (hw->chip_id != CHIP_ID_YUKON_EC_U)
+ dev->features |= NETIF_F_TSO;
if (highmem)
dev->features |= NETIF_F_HIGHDMA;
dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
+#ifdef SKY2_VLAN_TAG_USED
+ dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+ dev->vlan_rx_register = sky2_vlan_rx_register;
+ dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
+#endif
+
/* read the mac address */
memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
+ memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
/* device is off until link detection */
netif_carrier_off(dev);
{
struct net_device *dev, *dev1 = NULL;
struct sky2_hw *hw;
- int err, using_dac = 0;
+ int err, pm_cap, using_dac = 0;
err = pci_enable_device(pdev);
if (err) {
pci_set_master(pdev);
+ /* Find power-management capability. */
+ pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+ if (pm_cap == 0) {
+ printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
+ "aborting.\n");
+ err = -EIO;
+ goto err_out_free_regions;
+ }
+
if (sizeof(dma_addr_t) > sizeof(u32)) {
err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
if (!err)
}
}
#ifdef __BIG_ENDIAN
- /* byte swap decriptors in hardware */
+ /* byte swap descriptors in hardware */
{
u32 reg;
memset(hw, 0, sizeof(*hw));
hw->pdev = pdev;
- spin_lock_init(&hw->phy_lock);
hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
if (!hw->regs) {
pci_name(pdev));
goto err_out_free_hw;
}
+ hw->pm_cap = pm_cap;
err = sky2_reset(hw);
if (err)
goto err_out_iounmap;
- printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
- pci_resource_start(pdev, 0), pdev->irq,
- yukon_name[hw->chip_id - CHIP_ID_YUKON],
+ printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
+ DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
+ yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
hw->chip_id, hw->chip_rev);
dev = sky2_init_netdev(hw, 0, using_dac);
unregister_netdev(dev0);
sky2_write32(hw, B0_IMSK, 0);
+ sky2_set_power_state(hw, PCI_D3hot);
sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
sky2_write8(hw, B0_CTST, CS_RST_SET);
+ sky2_read8(hw, B0_CTST);
free_irq(pdev->irq, hw);
pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
free_netdev(dev0);
iounmap(hw->regs);
kfree(hw);
+
pci_set_drvdata(pdev, NULL);
}
static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct sky2_hw *hw = pci_get_drvdata(pdev);
- int i, wol = 0;
+ int i;
for (i = 0; i < 2; i++) {
struct net_device *dev = hw->dev[i];
if (dev) {
- struct sky2_port *sky2 = netdev_priv(dev);
- if (netif_running(dev)) {
- netif_carrier_off(dev);
- sky2_down(dev);
- }
+ if (!netif_running(dev))
+ continue;
+
+ sky2_down(dev);
netif_device_detach(dev);
- wol |= sky2->wol;
}
}
- pci_save_state(pdev);
- pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
- pci_disable_device(pdev);
- pci_set_power_state(pdev, pci_choose_state(pdev, state));
-
- return 0;
+ return sky2_set_power_state(hw, pci_choose_state(pdev, state));
}
static int sky2_resume(struct pci_dev *pdev)
struct sky2_hw *hw = pci_get_drvdata(pdev);
int i;
- pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
pci_enable_wake(pdev, PCI_D0, 0);
+ sky2_set_power_state(hw, PCI_D0);
sky2_reset(hw);
for (i = 0; i < 2; i++) {
struct net_device *dev = hw->dev[i];
if (dev) {
- netif_device_attach(dev);
- if (netif_running(dev))
+ if (netif_running(dev)) {
+ netif_device_attach(dev);
sky2_up(dev);
+ }
}
}
return 0;
static int __init sky2_init_module(void)
{
- return pci_module_init(&sky2_driver);
+ return pci_register_driver(&sky2_driver);
}
static void __exit sky2_cleanup_module(void)
MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff