u64 tx_mat0_n[0x8];
#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
- u8 unused_1[0x8];
+ u64 xmsi_mask_reg;
u64 stat_byte_cnt;
#define STAT_BC(n) vBIT(n,4,12)
u64 mdio_control;
#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
-#define MDIO_MMD_PMA_DEV_ADDR 0x1
-#define MDIO_MMD_PMD_DEV_ADDR 0x1
-#define MDIO_MMD_WIS_DEV_ADDR 0x2
-#define MDIO_MMD_PCS_DEV_ADDR 0x3
-#define MDIO_MMD_PHYXS_DEV_ADDR 0x4
#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
#define MDIO_OP(val) vBIT(val, 60, 2)
u64 rmac_cfg_key;
#define RMAC_CFG_KEY(val) vBIT(val,0,16)
-#define MAX_MAC_ADDRESSES 16
-#define MAX_MC_ADDRESSES 32 /* Multicast addresses */
-#define MAC_MAC_ADDR_START_OFFSET 0
-#define MAC_MC_ADDR_START_OFFSET 16
-#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
+#define S2IO_MAC_ADDR_START_OFFSET 0
+
+#define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */
+#define S2IO_HERC_MAX_MC_ADDRESSES 256
+
+#define S2IO_XENA_MAX_MAC_ADDRESSES 16
+#define S2IO_HERC_MAX_MAC_ADDRESSES 64
+
+#define S2IO_XENA_MC_ADDR_START_OFFSET 16
+#define S2IO_HERC_MC_ADDR_START_OFFSET 64
+
u64 rmac_addr_cmd_mem;
#define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
#define RMAC_ADDR_CMD_MEM_RD 0