#define OPCODE_OB_MAC_IOCB_FN0 0x01
#define OPCODE_OB_MAC_IOCB_FN2 0x21
-#define OPCODE_OB_TCP_IOCB_FN0 0x03
-#define OPCODE_OB_TCP_IOCB_FN2 0x23
-#define OPCODE_UPDATE_NCB_IOCB_FN0 0x00
-#define OPCODE_UPDATE_NCB_IOCB_FN2 0x20
-#define OPCODE_UPDATE_NCB_IOCB 0xF0
#define OPCODE_IB_MAC_IOCB 0xF9
+#define OPCODE_IB_3032_MAC_IOCB 0x09
#define OPCODE_IB_IP_IOCB 0xFA
-#define OPCODE_IB_TCP_IOCB 0xFB
-#define OPCODE_DUMP_PROTO_IOCB 0xFE
-#define OPCODE_BUFFER_ALERT_IOCB 0xFB
+#define OPCODE_IB_3032_IP_IOCB 0x0A
#define OPCODE_FUNC_ID_MASK 0x30
#define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
-#define OUTBOUND_TCP_IOCB 0x03 /* plus function bits */
-#define UPDATE_NCB_IOCB 0x00 /* plus function bits */
#define FN0_MA_BITS_MASK 0x00
#define FN1_MA_BITS_MASK 0x80
struct ob_mac_iocb_req {
u8 opcode;
u8 flags;
-#define OB_MAC_IOCB_REQ_MA 0xC0
-#define OB_MAC_IOCB_REQ_F 0x20
-#define OB_MAC_IOCB_REQ_X 0x10
+#define OB_MAC_IOCB_REQ_MA 0xe0
+#define OB_MAC_IOCB_REQ_F 0x10
+#define OB_MAC_IOCB_REQ_X 0x08
#define OB_MAC_IOCB_REQ_D 0x02
#define OB_MAC_IOCB_REQ_I 0x01
- __le16 reserved0;
+ u8 flags1;
+#define OB_3032MAC_IOCB_REQ_IC 0x04
+#define OB_3032MAC_IOCB_REQ_TC 0x02
+#define OB_3032MAC_IOCB_REQ_UC 0x01
+ u8 reserved0;
- __le32 transaction_id;
+ u32 transaction_id; /* opaque for hardware */
__le16 data_len;
- __le16 reserved1;
+ u8 ip_hdr_off;
+ u8 ip_hdr_len;
+ __le32 reserved1;
__le32 reserved2;
- __le32 reserved3;
__le32 buf_addr0_low;
__le32 buf_addr0_high;
__le32 buf_0_len;
__le32 buf_addr2_low;
__le32 buf_addr2_high;
__le32 buf_2_len;
+ __le32 reserved3;
__le32 reserved4;
- __le32 reserved5;
};
/*
* The following constants define control bits for buffer
u8 opcode;
u8 flags;
#define OB_MAC_IOCB_RSP_P 0x08
+#define OB_MAC_IOCB_RSP_L 0x04
#define OB_MAC_IOCB_RSP_S 0x02
#define OB_MAC_IOCB_RSP_I 0x01
__le16 reserved0;
- __le32 transaction_id;
+ u32 transaction_id; /* opaque for hardware */
__le32 reserved1;
__le32 reserved2;
};
struct ib_mac_iocb_rsp {
u8 opcode;
+#define IB_MAC_IOCB_RSP_V 0x80
u8 flags;
#define IB_MAC_IOCB_RSP_S 0x80
#define IB_MAC_IOCB_RSP_H1 0x40
struct ob_ip_iocb_rsp {
u8 opcode;
u8 flags;
+#define OB_MAC_IOCB_RSP_H 0x10
#define OB_MAC_IOCB_RSP_E 0x08
#define OB_MAC_IOCB_RSP_L 0x04
#define OB_MAC_IOCB_RSP_S 0x02
__le32 reserved2;
};
-struct ob_tcp_iocb_req {
- u8 opcode;
-
- u8 flags0;
-#define OB_TCP_IOCB_REQ_P 0x80
-#define OB_TCP_IOCB_REQ_CI 0x20
-#define OB_TCP_IOCB_REQ_H 0x10
-#define OB_TCP_IOCB_REQ_LN 0x08
-#define OB_TCP_IOCB_REQ_K 0x04
-#define OB_TCP_IOCB_REQ_D 0x02
-#define OB_TCP_IOCB_REQ_I 0x01
-
- u8 flags1;
-#define OB_TCP_IOCB_REQ_OSM 0x40
-#define OB_TCP_IOCB_REQ_URG 0x20
-#define OB_TCP_IOCB_REQ_ACK 0x10
-#define OB_TCP_IOCB_REQ_PSH 0x08
-#define OB_TCP_IOCB_REQ_RST 0x04
-#define OB_TCP_IOCB_REQ_SYN 0x02
-#define OB_TCP_IOCB_REQ_FIN 0x01
-
- u8 options_len;
-#define OB_TCP_IOCB_REQ_OMASK 0xF0
-#define OB_TCP_IOCB_REQ_SHIFT 4
-
- __le32 transaction_id;
- __le32 data_len;
- __le32 hncb_ptr_low;
- __le32 hncb_ptr_high;
- __le32 buf_addr0_low;
- __le32 buf_addr0_high;
- __le32 buf_0_len;
- __le32 buf_addr1_low;
- __le32 buf_addr1_high;
- __le32 buf_1_len;
- __le32 buf_addr2_low;
- __le32 buf_addr2_high;
- __le32 buf_2_len;
- __le32 time_stamp;
- __le32 reserved1;
-};
-
-struct ob_tcp_iocb_rsp {
- u8 opcode;
-
- u8 flags0;
-#define OB_TCP_IOCB_RSP_C 0x20
-#define OB_TCP_IOCB_RSP_H 0x10
-#define OB_TCP_IOCB_RSP_LN 0x08
-#define OB_TCP_IOCB_RSP_K 0x04
-#define OB_TCP_IOCB_RSP_D 0x02
-#define OB_TCP_IOCB_RSP_I 0x01
-
- u8 flags1;
-#define OB_TCP_IOCB_RSP_E 0x10
-#define OB_TCP_IOCB_RSP_W 0x08
-#define OB_TCP_IOCB_RSP_P 0x04
-#define OB_TCP_IOCB_RSP_T 0x02
-#define OB_TCP_IOCB_RSP_F 0x01
-
- u8 state;
-#define OB_TCP_IOCB_RSP_SMASK 0xF0
-#define OB_TCP_IOCB_RSP_SHIFT 4
-
- __le32 transaction_id;
- __le32 local_ncb_ptr;
- __le32 reserved0;
-};
-
struct ib_ip_iocb_rsp {
u8 opcode;
+#define IB_IP_IOCB_RSP_3032_V 0x80
+#define IB_IP_IOCB_RSP_3032_O 0x40
+#define IB_IP_IOCB_RSP_3032_I 0x20
+#define IB_IP_IOCB_RSP_3032_R 0x10
u8 flags;
#define IB_IP_IOCB_RSP_S 0x80
#define IB_IP_IOCB_RSP_H1 0x40
__le16 length;
__le16 checksum;
+#define IB_IP_IOCB_RSP_3032_ICE 0x01
+#define IB_IP_IOCB_RSP_3032_CE 0x02
+#define IB_IP_IOCB_RSP_3032_NUC 0x04
+#define IB_IP_IOCB_RSP_3032_UDP 0x08
+#define IB_IP_IOCB_RSP_3032_TCP 0x10
+#define IB_IP_IOCB_RSP_3032_IPE 0x20
__le16 reserved;
#define IB_IP_IOCB_RSP_R 0x01
__le32 ial_low;
__le32 ial_high;
};
-struct ib_tcp_iocb_rsp {
- u8 opcode;
- u8 flags;
-#define IB_TCP_IOCB_RSP_P 0x80
-#define IB_TCP_IOCB_RSP_T 0x40
-#define IB_TCP_IOCB_RSP_D 0x20
-#define IB_TCP_IOCB_RSP_N 0x10
-#define IB_TCP_IOCB_RSP_IP 0x03
-#define IB_TCP_FLAG_MASK 0xf0
-#define IB_TCP_FLAG_IOCB_SYN 0x00
-
-#define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
-
- __le16 length;
- __le32 hncb_ref_num;
- __le32 ial_low;
- __le32 ial_high;
-};
-
struct net_rsp_iocb {
u8 opcode;
u8 flags;
#define MII_SCAN_REGISTER 0x00000001
+#define PHY_ID_0_REG 2
+#define PHY_ID_1_REG 3
+
+#define PHY_OUI_1_MASK 0xfc00
+#define PHY_MODEL_MASK 0x03f0
+
+/* Address for the Agere Phy */
+#define MII_AGERE_ADDR_1 0x00001000
+#define MII_AGERE_ADDR_2 0x00001100
+
/* 32-bit ispControlStatus */
enum {
ISP_CONTROL_NP_MASK = 0x0003,
IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
+ IP_ADDR_INDEX_REG_6 = 0x0008,
+ IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
+ IP_ADDR_INDEX_REG_E = 0x0040,
+};
+enum {
+ QL3032_PORT_CONTROL_DS = 0x0001,
+ QL3032_PORT_CONTROL_HH = 0x0002,
+ QL3032_PORT_CONTROL_EIv6 = 0x0004,
+ QL3032_PORT_CONTROL_EIv4 = 0x0008,
+ QL3032_PORT_CONTROL_ET = 0x0010,
+ QL3032_PORT_CONTROL_EF = 0x0020,
+ QL3032_PORT_CONTROL_DRM = 0x0040,
+ QL3032_PORT_CONTROL_RLB = 0x0080,
+ QL3032_PORT_CONTROL_RCB = 0x0100,
+ QL3032_PORT_CONTROL_KIE = 0x0200,
};
enum {
u32 internalRamWDataReg;
u32 reclaimedBufferAddrRegLow;
u32 reclaimedBufferAddrRegHigh;
- u32 reserved[2];
+ u32 tcpConfiguration;
+ u32 functionControl;
u32 fpgaRevID;
u32 localRamAddr;
u32 localRamDataAutoIncr;
PHY_CTRL_LOOPBACK = 0x4000,
PETBI_CONTROL_REG = 0x00,
+ PETBI_CTRL_ALL_PARAMS = 0x7140,
PETBI_CTRL_SOFT_RESET = 0x8000,
PETBI_CTRL_AUTO_NEG = 0x1000,
PETBI_CTRL_RESTART_NEG = 0x0200,
PETBI_EXPANSION_REG = 0x06,
PETBI_EXP_PAGE_RX = 0x0002,
+ PHY_GIG_CONTROL = 9,
+ PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
+ PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/
+ PHY_GIG_ALL_PARAMS = 0x0300,
+ PHY_GIG_ADV_1000F = 0x0200,
+ PHY_GIG_ADV_1000H = 0x0100,
+
+ PHY_NEG_ADVER = 4,
+ PHY_NEG_ALL_PARAMS = 0x0fe0,
+ PHY_NEG_ASY_PAUSE = 0x0800,
+ PHY_NEG_SYM_PAUSE = 0x0400,
+ PHY_NEG_ADV_SPEED = 0x01e0,
+ PHY_NEG_ADV_100F = 0x0100,
+ PHY_NEG_ADV_100H = 0x0080,
+ PHY_NEG_ADV_10F = 0x0040,
+ PHY_NEG_ADV_10H = 0x0020,
+
PETBI_TBI_CTRL = 0x11,
PETBI_TBI_RESET = 0x8000,
PETBI_TBI_AUTO_SENSE = 0x0100,
PHY_AUX_RESET_STICK = 0x0002,
PHY_NEG_PAUSE = 0x0400,
PHY_CTRL_SOFT_RESET = 0x8000,
- PHY_NEG_ADVER = 4,
- PHY_NEG_ADV_SPEED = 0x01e0,
+ PHY_CTRL_AUTO_NEG = 0x1000,
PHY_CTRL_RESTART_NEG = 0x0200,
};
enum {
u16 pauseThreshold_mac;
u16 resumeThreshold_mac;
u16 portConfiguration;
+#define PORT_CONFIG_DEFAULT 0xf700
#define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
#define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
#define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
*/
struct eeprom_function_cfg {
u8 reserved[30];
- u8 macAddress[6];
- u8 macAddressSecondary[6];
+ u16 macAddress[3];
+ u16 macAddressSecondary[3];
u16 subsysVendorId;
u16 subsysDeviceId;
*/
struct eeprom_data {
u8 asicId[4];
- u8 version;
- u8 numPorts;
+ u16 version_and_numPorts; /* together to avoid endianness crap */
u16 boardId;
#define EEPROM_BOARDID_STR_SIZE 16
#define QL3XXX_VENDOR_ID 0x1077
#define QL3022_DEVICE_ID 0x3022
+#define QL3032_DEVICE_ID 0x3032
/* MTU & Frame Size stuff */
#define NORMAL_MTU_SIZE ETH_DATA_LEN
/* Transmit and Receive Buffers */
#define NUM_LBUFQ_ENTRIES 128
+#define JUMBO_NUM_LBUFQ_ENTRIES 32
#define NUM_SBUFQ_ENTRIES 64
#define QL_SMALL_BUFFER_SIZE 32
#define QL_ADDR_ELE_PER_BUFQ_ENTRY \
(sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
/* Each send has at least control block. This is how many we keep. */
#define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
-#define NUM_LARGE_BUFFERS NUM_LBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
+
#define QL_HEADER_SPACE 32 /* make header space at top of skb. */
/*
* Large & Small Buffers for Receives
*/
struct lrg_buf_q_entry {
- u32 addr0_lower;
+ __le32 addr0_lower;
#define IAL_LAST_ENTRY 0x00000001
#define IAL_CONT_ENTRY 0x00000002
#define IAL_FLAG_MASK 0x00000003
- u32 addr0_upper;
- u32 addr1_lower;
- u32 addr1_upper;
- u32 addr2_lower;
- u32 addr2_upper;
- u32 addr3_lower;
- u32 addr3_upper;
- u32 addr4_lower;
- u32 addr4_upper;
- u32 addr5_lower;
- u32 addr5_upper;
- u32 addr6_lower;
- u32 addr6_upper;
- u32 addr7_lower;
- u32 addr7_upper;
+ __le32 addr0_upper;
+ __le32 addr1_lower;
+ __le32 addr1_upper;
+ __le32 addr2_lower;
+ __le32 addr2_upper;
+ __le32 addr3_lower;
+ __le32 addr3_upper;
+ __le32 addr4_lower;
+ __le32 addr4_upper;
+ __le32 addr5_lower;
+ __le32 addr5_upper;
+ __le32 addr6_lower;
+ __le32 addr6_upper;
+ __le32 addr7_lower;
+ __le32 addr7_upper;
};
struct bufq_addr_element {
- u32 addr_low;
- u32 addr_high;
+ __le32 addr_low;
+ __le32 addr_high;
};
#define QL_NO_RESET 0
int index;
};
+/*
+ * Original IOCB has 3 sg entries:
+ * first points to skb-data area
+ * second points to first frag
+ * third points to next oal.
+ * OAL has 5 entries:
+ * 1 thru 4 point to frags
+ * fifth points to next oal.
+ */
+#define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
+
+struct oal_entry {
+ __le32 dma_lo;
+ __le32 dma_hi;
+ __le32 len;
+#define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
+#define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
+};
+
+struct oal {
+ struct oal_entry oal_entry[5];
+};
+
+struct map_list {
+ DECLARE_PCI_UNMAP_ADDR(mapaddr);
+ DECLARE_PCI_UNMAP_LEN(maplen);
+};
+
struct ql_tx_buf_cb {
struct sk_buff *skb;
struct ob_mac_iocb_req *queue_entry ;
- DECLARE_PCI_UNMAP_ADDR(mapaddr);
- DECLARE_PCI_UNMAP_LEN(maplen);
+ int seg_count;
+ struct oal *oal;
+ struct map_list map[MAX_SKB_FRAGS+1];
};
/* definitions for type field */
struct pci_dev *pdev;
struct net_device *ndev; /* Parent NET device */
+ struct napi_struct napi;
+
/* Hardware information */
u8 chip_rev_id;
u8 pci_slot;
struct net_rsp_iocb *rsp_current;
u16 rsp_consumer_index;
u16 reserved_06;
- u32 *prsp_producer_index;
+ volatile __le32 *prsp_producer_index;
u32 rsp_producer_index_phy_addr_high;
u32 rsp_producer_index_phy_addr_low;
u32 lrg_buf_q_producer_index;
u32 lrg_buf_release_cnt;
struct bufq_addr_element *lrg_buf_next_free;
+ u32 num_large_buffers;
+ u32 num_lbufq_entries;
/* Large (Receive) Buffers */
- struct ql_rcv_buf_cb lrg_buf[NUM_LARGE_BUFFERS];
+ struct ql_rcv_buf_cb *lrg_buf;
struct ql_rcv_buf_cb *lrg_buf_free_head;
struct ql_rcv_buf_cb *lrg_buf_free_tail;
u32 lrg_buf_free_count;
u32 small_buf_release_cnt;
u32 small_buf_total_size;
- /* ISR related, saves status for DPC. */
- u32 control_status;
-
struct eeprom_data nvram_data;
- struct timer_list ioctl_timer;
u32 port_link_state;
- u32 last_rsp_offset;
/* 4022 specific */
u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
u32 mac_ob_opcode; /* Opcode to use on mac transmission */
- u32 tcp_ob_opcode; /* Opcode to use on tcp transmission */
- u32 update_ob_opcode; /* Opcode to use for updating NCB */
u32 mb_bit_mask; /* MA Bits mask to use on transmission */
u32 numPorts;
- struct net_device_stats stats;
struct workqueue_struct *workqueue;
- struct work_struct reset_work;
- struct work_struct tx_timeout_work;
+ struct delayed_work reset_work;
+ struct delayed_work tx_timeout_work;
+ struct delayed_work link_state_work;
u32 max_frame_size;
+ u32 device_id;
+ u16 phyType;
};
#endif /* _QLA3XXX_H_ */
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff