#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/in.h>
+#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/udp.h>
#include <linux/etherdevice.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
-#include <linux/mii.h>
+#include <linux/phy.h>
#include <linux/mv643xx_eth.h>
-#include <asm/io.h>
-#include <asm/types.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/inet_lro.h>
#include <asm/system.h>
static char mv643xx_eth_driver_name[] = "mv643xx_eth";
-static char mv643xx_eth_driver_version[] = "1.0";
+static char mv643xx_eth_driver_version[] = "1.4";
-#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
-#define MV643XX_ETH_NAPI
-#define MV643XX_ETH_TX_FAST_REFILL
-#undef MV643XX_ETH_COAL
-
-#define MV643XX_ETH_TX_COAL 100
-#ifdef MV643XX_ETH_COAL
-#define MV643XX_ETH_RX_COAL 100
-#endif
-
-#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
-#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
-#else
-#define MAX_DESCS_PER_SKB 1
-#endif
-
-#define ETH_HW_IP_ALIGN 2
/*
* Registers shared between all ports.
*/
#define PHY_ADDR 0x0000
#define SMI_REG 0x0004
+#define SMI_BUSY 0x10000000
+#define SMI_READ_VALID 0x08000000
+#define SMI_OPCODE_READ 0x04000000
+#define SMI_OPCODE_WRITE 0x00000000
+#define ERR_INT_CAUSE 0x0080
+#define ERR_INT_SMI_DONE 0x00000010
+#define ERR_INT_MASK 0x0084
#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
/*
- * Per-port registers.
+ * Main per-port registers. These live at offset 0x0400 for
+ * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
*/
-#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
+#define PORT_CONFIG 0x0000
#define UNICAST_PROMISCUOUS_MODE 0x00000001
-#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
-#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
-#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
-#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
-#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
-#define PORT_STATUS(p) (0x0444 + ((p) << 10))
+#define PORT_CONFIG_EXT 0x0004
+#define MAC_ADDR_LOW 0x0014
+#define MAC_ADDR_HIGH 0x0018
+#define SDMA_CONFIG 0x001c
+#define PORT_SERIAL_CONTROL 0x003c
+#define PORT_STATUS 0x0044
#define TX_FIFO_EMPTY 0x00000400
-#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
-#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
-#define INT_CAUSE(p) (0x0460 + ((p) << 10))
-#define INT_RX 0x00000804
+#define TX_IN_PROGRESS 0x00000080
+#define PORT_SPEED_MASK 0x00000030
+#define PORT_SPEED_1000 0x00000010
+#define PORT_SPEED_100 0x00000020
+#define PORT_SPEED_10 0x00000000
+#define FLOW_CONTROL_ENABLED 0x00000008
+#define FULL_DUPLEX 0x00000004
+#define LINK_UP 0x00000002
+#define TXQ_COMMAND 0x0048
+#define TXQ_FIX_PRIO_CONF 0x004c
+#define TX_BW_RATE 0x0050
+#define TX_BW_MTU 0x0058
+#define TX_BW_BURST 0x005c
+#define INT_CAUSE 0x0060
+#define INT_TX_END 0x07f80000
+#define INT_RX 0x000003fc
#define INT_EXT 0x00000002
-#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
-#define INT_EXT_LINK 0x00100000
-#define INT_EXT_PHY 0x00010000
-#define INT_EXT_TX_ERROR_0 0x00000100
-#define INT_EXT_TX_0 0x00000001
-#define INT_EXT_TX 0x00000101
-#define INT_MASK(p) (0x0468 + ((p) << 10))
-#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
-#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
-#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
-#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
-#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
+#define INT_CAUSE_EXT 0x0064
+#define INT_EXT_LINK_PHY 0x00110000
+#define INT_EXT_TX 0x000000ff
+#define INT_MASK 0x0068
+#define INT_MASK_EXT 0x006c
+#define TX_FIFO_URGENT_THRESHOLD 0x0074
+#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
+#define TX_BW_RATE_MOVED 0x00e0
+#define TX_BW_MTU_MOVED 0x00e8
+#define TX_BW_BURST_MOVED 0x00ec
+#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
+#define RXQ_COMMAND 0x0280
+#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
+#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
+#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
+#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
+
+/*
+ * Misc per-port registers.
+ */
#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
* SDMA configuration register.
*/
#define RX_BURST_SIZE_4_64BIT (2 << 1)
+#define RX_BURST_SIZE_16_64BIT (4 << 1)
#define BLM_RX_NO_SWAP (1 << 4)
#define BLM_TX_NO_SWAP (1 << 5)
#define TX_BURST_SIZE_4_64BIT (2 << 22)
+#define TX_BURST_SIZE_16_64BIT (4 << 22)
#if defined(__BIG_ENDIAN)
#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
- RX_BURST_SIZE_4_64BIT | \
- TX_BURST_SIZE_4_64BIT
+ (RX_BURST_SIZE_4_64BIT | \
+ TX_BURST_SIZE_4_64BIT)
#elif defined(__LITTLE_ENDIAN)
#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
- RX_BURST_SIZE_4_64BIT | \
- BLM_RX_NO_SWAP | \
- BLM_TX_NO_SWAP | \
- TX_BURST_SIZE_4_64BIT
+ (RX_BURST_SIZE_4_64BIT | \
+ BLM_RX_NO_SWAP | \
+ BLM_TX_NO_SWAP | \
+ TX_BURST_SIZE_4_64BIT)
#else
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
#endif
#define SET_MII_SPEED_TO_100 (1 << 24)
#define SET_GMII_SPEED_TO_1000 (1 << 23)
#define SET_FULL_DUPLEX_MODE (1 << 21)
-#define MAX_RX_PACKET_1522BYTE (1 << 17)
#define MAX_RX_PACKET_9700BYTE (5 << 17)
-#define MAX_RX_PACKET_MASK (7 << 17)
#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
#define FORCE_LINK_PASS (1 << 1)
#define SERIAL_PORT_ENABLE (1 << 0)
-#define DEFAULT_RX_QUEUE_SIZE 400
-#define DEFAULT_TX_QUEUE_SIZE 800
-
-/* SMI reg */
-#define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
-#define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
-#define SMI_OPCODE_WRITE 0 /* Completion of Read */
-#define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
+#define DEFAULT_RX_QUEUE_SIZE 128
+#define DEFAULT_TX_QUEUE_SIZE 256
/*
#define RX_ENABLE_INTERRUPT 0x20000000
#define RX_FIRST_DESC 0x08000000
#define RX_LAST_DESC 0x04000000
+#define RX_IP_HDR_OK 0x02000000
+#define RX_PKT_IS_IPV4 0x01000000
+#define RX_PKT_IS_ETHERNETV2 0x00800000
+#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
+#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
+#define RX_PKT_IS_VLAN_TAGGED 0x00080000
/* TX descriptor command */
#define TX_ENABLE_INTERRUPT 0x00800000
#define GEN_IP_V4_CHECKSUM 0x00040000
#define GEN_TCP_UDP_CHECKSUM 0x00020000
#define UDP_FRAME 0x00010000
+#define MAC_HDR_EXTRA_4_BYTES 0x00008000
+#define MAC_HDR_EXTRA_8_BYTES 0x00000200
#define TX_IHL_SHIFT 11
/* global *******************************************************************/
struct mv643xx_eth_shared_private {
+ /*
+ * Ethernet controller base address.
+ */
void __iomem *base;
- /* used to protect SMI_REG, which is shared across ports */
- spinlock_t phy_lock;
+ /*
+ * Points at the right SMI instance to use.
+ */
+ struct mv643xx_eth_shared_private *smi;
+
+ /*
+ * Provides access to local SMI interface.
+ */
+ struct mii_bus *smi_bus;
+
+ /*
+ * If we have access to the error interrupt pin (which is
+ * somewhat misnamed as it not only reflects internal errors
+ * but also reflects SMI completion), use that to wait for
+ * SMI access completion instead of polling the SMI busy bit.
+ */
+ int err_interrupt;
+ wait_queue_head_t smi_busy_wait;
+ /*
+ * Per-port MBUS window access register value.
+ */
u32 win_protect;
+ /*
+ * Hardware-specific parameters.
+ */
unsigned int t_clk;
+ int extended_rx_coal_limit;
+ int tx_bw_control;
};
+#define TX_BW_CONTROL_ABSENT 0
+#define TX_BW_CONTROL_OLD_LAYOUT 1
+#define TX_BW_CONTROL_NEW_LAYOUT 2
+
+static int mv643xx_eth_open(struct net_device *dev);
+static int mv643xx_eth_stop(struct net_device *dev);
+
/* per-port *****************************************************************/
struct mib_counters {
u32 late_collision;
};
+struct lro_counters {
+ u32 lro_aggregated;
+ u32 lro_flushed;
+ u32 lro_no_desc;
+};
+
struct rx_queue {
+ int index;
+
int rx_ring_size;
int rx_desc_count;
int rx_desc_area_size;
struct sk_buff **rx_skb;
- struct timer_list rx_oom;
+ struct net_lro_mgr lro_mgr;
+ struct net_lro_desc lro_arr[8];
};
-struct mv643xx_eth_private {
- struct mv643xx_eth_shared_private *shared;
- int port_num; /* User Ethernet port number */
-
- struct mv643xx_eth_shared_private *shared_smi;
-
- u32 tx_sram_addr; /* Base address of tx sram area */
- u32 tx_sram_size; /* Size of tx sram area */
+struct tx_queue {
+ int index;
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available and first returning Tx resource */
- int tx_curr_desc, tx_used_desc;
+ int tx_ring_size;
-#ifdef MV643XX_ETH_TX_FAST_REFILL
- u32 tx_clean_threshold;
-#endif
+ int tx_desc_count;
+ int tx_curr_desc;
+ int tx_used_desc;
struct tx_desc *tx_desc_area;
dma_addr_t tx_desc_dma;
int tx_desc_area_size;
- struct sk_buff **tx_skb;
- struct work_struct tx_timeout_task;
+ struct sk_buff_head tx_skb;
+
+ unsigned long tx_packets;
+ unsigned long tx_bytes;
+ unsigned long tx_dropped;
+};
+
+struct mv643xx_eth_private {
+ struct mv643xx_eth_shared_private *shared;
+ void __iomem *base;
+ int port_num;
struct net_device *dev;
+
+ struct phy_device *phy;
+
+ struct timer_list mib_counters_timer;
+ spinlock_t mib_counters_lock;
struct mib_counters mib_counters;
- spinlock_t lock;
- /* Size of Tx Ring per queue */
- int tx_ring_size;
- /* Number of tx descriptors in use */
- int tx_desc_count;
- u32 rx_int_coal;
- u32 tx_int_coal;
- struct mii_if_info mii;
+ struct lro_counters lro_counters;
+
+ struct work_struct tx_timeout_task;
+
+ struct napi_struct napi;
+ u8 oom;
+ u8 work_link;
+ u8 work_tx;
+ u8 work_tx_end;
+ u8 work_rx;
+ u8 work_rx_refill;
+
+ int skb_size;
+ struct sk_buff_head rx_recycle;
/*
* RX state.
*/
- int default_rx_ring_size;
+ int rx_ring_size;
unsigned long rx_desc_sram_addr;
int rx_desc_sram_size;
- struct napi_struct napi;
- struct rx_queue rxq[1];
+ int rxq_count;
+ struct timer_list rx_oom;
+ struct rx_queue rxq[8];
+
+ /*
+ * TX state.
+ */
+ int tx_ring_size;
+ unsigned long tx_desc_sram_addr;
+ int tx_desc_sram_size;
+ int txq_count;
+ struct tx_queue txq[8];
};
return readl(mp->shared->base + offset);
}
+static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
+{
+ return readl(mp->base + offset);
+}
+
static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
{
writel(data, mp->shared->base + offset);
}
+static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
+{
+ writel(data, mp->base + offset);
+}
+
/* rxq/txq helper functions *************************************************/
static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
{
- return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
+ return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
+}
+
+static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
+{
+ return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
}
static void rxq_enable(struct rx_queue *rxq)
{
struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
- wrl(mp, RXQ_COMMAND(mp->port_num), 1);
+ wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
}
static void rxq_disable(struct rx_queue *rxq)
{
struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
- u8 mask = 1;
+ u8 mask = 1 << rxq->index;
- wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
- while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
+ wrlp(mp, RXQ_COMMAND, mask << 8);
+ while (rdlp(mp, RXQ_COMMAND) & mask)
udelay(10);
}
-static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
- unsigned int queues)
+static void txq_reset_hw_ptr(struct tx_queue *txq)
{
- wrl(mp, TXQ_COMMAND(mp->port_num), queues);
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ u32 addr;
+
+ addr = (u32)txq->tx_desc_dma;
+ addr += txq->tx_curr_desc * sizeof(struct tx_desc);
+ wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
}
-static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
+static void txq_enable(struct tx_queue *txq)
{
- unsigned int port_num = mp->port_num;
- u32 queues;
-
- /* Stop Tx port activity. Check port Tx activity. */
- queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
- if (queues) {
- /* Issue stop command for active queues only */
- wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
-
- /* Wait for all Tx activity to terminate. */
- /* Check port cause register that all Tx queues are stopped */
- while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
- udelay(10);
-
- /* Wait for Tx FIFO to empty */
- while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
- udelay(10);
- }
-
- return queues;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ wrlp(mp, TXQ_COMMAND, 1 << txq->index);
}
-
-/* rx ***********************************************************************/
-static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
-
-static void rxq_refill(struct rx_queue *rxq)
+static void txq_disable(struct tx_queue *txq)
{
- struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
- unsigned long flags;
-
- spin_lock_irqsave(&mp->lock, flags);
-
- while (rxq->rx_desc_count < rxq->rx_ring_size) {
- int skb_size;
- struct sk_buff *skb;
- int unaligned;
- int rx;
-
- /*
- * Reserve 2+14 bytes for an ethernet header (the
- * hardware automatically prepends 2 bytes of dummy
- * data to each received packet), 4 bytes for a VLAN
- * header, and 4 bytes for the trailing FCS -- 24
- * bytes total.
- */
- skb_size = mp->dev->mtu + 24;
-
- skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
- if (skb == NULL)
- break;
-
- unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
- if (unaligned)
- skb_reserve(skb, dma_get_cache_alignment() - unaligned);
-
- rxq->rx_desc_count++;
- rx = rxq->rx_used_desc;
- rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ u8 mask = 1 << txq->index;
- rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
- skb_size, DMA_FROM_DEVICE);
- rxq->rx_desc_area[rx].buf_size = skb_size;
- rxq->rx_skb[rx] = skb;
- wmb();
- rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
- RX_ENABLE_INTERRUPT;
- wmb();
+ wrlp(mp, TXQ_COMMAND, mask << 8);
+ while (rdlp(mp, TXQ_COMMAND) & mask)
+ udelay(10);
+}
- skb_reserve(skb, ETH_HW_IP_ALIGN);
- }
+static void txq_maybe_wake(struct tx_queue *txq)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
- if (rxq->rx_desc_count == 0) {
- rxq->rx_oom.expires = jiffies + (HZ / 10);
- add_timer(&rxq->rx_oom);
+ if (netif_tx_queue_stopped(nq)) {
+ __netif_tx_lock(nq, smp_processor_id());
+ if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
+ netif_tx_wake_queue(nq);
+ __netif_tx_unlock(nq);
}
-
- spin_unlock_irqrestore(&mp->lock, flags);
}
-static inline void rxq_refill_timer_wrapper(unsigned long data)
+
+/* rx napi ******************************************************************/
+static int
+mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
+ u64 *hdr_flags, void *priv)
{
- rxq_refill((struct rx_queue *)data);
+ unsigned long cmd_sts = (unsigned long)priv;
+
+ /*
+ * Make sure that this packet is Ethernet II, is not VLAN
+ * tagged, is IPv4, has a valid IP header, and is TCP.
+ */
+ if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
+ RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
+ RX_PKT_IS_VLAN_TAGGED)) !=
+ (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
+ RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
+ return -1;
+
+ skb_reset_network_header(skb);
+ skb_set_transport_header(skb, ip_hdrlen(skb));
+ *iphdr = ip_hdr(skb);
+ *tcph = tcp_hdr(skb);
+ *hdr_flags = LRO_IPV4 | LRO_TCP;
+
+ return 0;
}
static int rxq_process(struct rx_queue *rxq, int budget)
{
struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
struct net_device_stats *stats = &mp->dev->stats;
+ int lro_flush_needed;
int rx;
+ lro_flush_needed = 0;
rx = 0;
- while (rx < budget) {
- struct sk_buff *skb;
- volatile struct rx_desc *rx_desc;
+ while (rx < budget && rxq->rx_desc_count) {
+ struct rx_desc *rx_desc;
unsigned int cmd_sts;
- unsigned long flags;
-
- spin_lock_irqsave(&mp->lock, flags);
+ struct sk_buff *skb;
+ u16 byte_cnt;
rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
cmd_sts = rx_desc->cmd_sts;
- if (cmd_sts & BUFFER_OWNED_BY_DMA) {
- spin_unlock_irqrestore(&mp->lock, flags);
+ if (cmd_sts & BUFFER_OWNED_BY_DMA)
break;
- }
rmb();
skb = rxq->rx_skb[rxq->rx_curr_desc];
rxq->rx_skb[rxq->rx_curr_desc] = NULL;
- rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
+ rxq->rx_curr_desc++;
+ if (rxq->rx_curr_desc == rxq->rx_ring_size)
+ rxq->rx_curr_desc = 0;
- spin_unlock_irqrestore(&mp->lock, flags);
-
- dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
- mp->dev->mtu + 24, DMA_FROM_DEVICE);
+ dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
+ rx_desc->buf_size, DMA_FROM_DEVICE);
rxq->rx_desc_count--;
rx++;
+ mp->work_rx_refill |= 1 << rxq->index;
+
+ byte_cnt = rx_desc->byte_cnt;
+
/*
* Update statistics.
- * Note byte count includes 4 byte CRC count
+ *
+ * Note that the descriptor byte count includes 2 dummy
+ * bytes automatically inserted by the hardware at the
+ * start of the packet (which we don't count), and a 4
+ * byte CRC at the end of the packet (which we do count).
*/
stats->rx_packets++;
- stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
+ stats->rx_bytes += byte_cnt - 2;
/*
- * In case received a packet without first / last bits on OR
- * the error summary bit is on, the packets needs to be dropeed.
+ * In case we received a packet without first / last bits
+ * on, or the error summary bit is set, the packet needs
+ * to be dropped.
*/
- if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
- (RX_FIRST_DESC | RX_LAST_DESC))
- || (cmd_sts & ERROR_SUMMARY)) {
- stats->rx_dropped++;
- if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
- (RX_FIRST_DESC | RX_LAST_DESC)) {
- if (net_ratelimit())
- printk(KERN_ERR
- "%s: Received packet spread "
- "on multiple descriptors\n",
- mp->dev->name);
- }
- if (cmd_sts & ERROR_SUMMARY)
- stats->rx_errors++;
+ if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
+ != (RX_FIRST_DESC | RX_LAST_DESC))
+ goto err;
- dev_kfree_skb_irq(skb);
- } else {
- /*
- * The -4 is for the CRC in the trailer of the
- * received packet
- */
- skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
-
- if (cmd_sts & LAYER_4_CHECKSUM_OK) {
- skb->ip_summed = CHECKSUM_UNNECESSARY;
- skb->csum = htons(
- (cmd_sts & 0x0007fff8) >> 3);
- }
- skb->protocol = eth_type_trans(skb, mp->dev);
-#ifdef MV643XX_ETH_NAPI
+ /*
+ * The -4 is for the CRC in the trailer of the
+ * received packet
+ */
+ skb_put(skb, byte_cnt - 2 - 4);
+
+ if (cmd_sts & LAYER_4_CHECKSUM_OK)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ skb->protocol = eth_type_trans(skb, mp->dev);
+
+ if (skb->dev->features & NETIF_F_LRO &&
+ skb->ip_summed == CHECKSUM_UNNECESSARY) {
+ lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
+ lro_flush_needed = 1;
+ } else
netif_receive_skb(skb);
-#else
- netif_rx(skb);
-#endif
+
+ continue;
+
+err:
+ stats->rx_dropped++;
+
+ if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
+ (RX_FIRST_DESC | RX_LAST_DESC)) {
+ if (net_ratelimit())
+ dev_printk(KERN_ERR, &mp->dev->dev,
+ "received packet spanning "
+ "multiple descriptors\n");
}
- mp->dev->last_rx = jiffies;
+
+ if (cmd_sts & ERROR_SUMMARY)
+ stats->rx_errors++;
+
+ dev_kfree_skb(skb);
}
- rxq_refill(rxq);
+
+ if (lro_flush_needed)
+ lro_flush_all(&rxq->lro_mgr);
+
+ if (rx < budget)
+ mp->work_rx &= ~(1 << rxq->index);
return rx;
}
-#ifdef MV643XX_ETH_NAPI
-static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
+static int rxq_refill(struct rx_queue *rxq, int budget)
{
- struct mv643xx_eth_private *mp;
- int rx;
+ struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
+ int refilled;
- mp = container_of(napi, struct mv643xx_eth_private, napi);
+ refilled = 0;
+ while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
+ struct sk_buff *skb;
+ int unaligned;
+ int rx;
+ struct rx_desc *rx_desc;
-#ifdef MV643XX_ETH_TX_FAST_REFILL
- if (++mp->tx_clean_threshold > 5) {
- mv643xx_eth_free_completed_tx_descs(mp->dev);
- mp->tx_clean_threshold = 0;
- }
-#endif
+ skb = __skb_dequeue(&mp->rx_recycle);
+ if (skb == NULL)
+ skb = dev_alloc_skb(mp->skb_size +
+ dma_get_cache_alignment() - 1);
+
+ if (skb == NULL) {
+ mp->oom = 1;
+ goto oom;
+ }
+
+ unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
+ if (unaligned)
+ skb_reserve(skb, dma_get_cache_alignment() - unaligned);
+
+ refilled++;
+ rxq->rx_desc_count++;
+
+ rx = rxq->rx_used_desc++;
+ if (rxq->rx_used_desc == rxq->rx_ring_size)
+ rxq->rx_used_desc = 0;
- rx = rxq_process(mp->rxq, budget);
+ rx_desc = rxq->rx_desc_area + rx;
+
+ rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
+ skb->data, mp->skb_size,
+ DMA_FROM_DEVICE);
+ rx_desc->buf_size = mp->skb_size;
+ rxq->rx_skb[rx] = skb;
+ wmb();
+ rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
+ wmb();
- if (rx < budget) {
- netif_rx_complete(mp->dev, napi);
- wrl(mp, INT_CAUSE(mp->port_num), 0);
- wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
- wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
+ /*
+ * The hardware automatically prepends 2 bytes of
+ * dummy data to each received packet, so that the
+ * IP header ends up 16-byte aligned.
+ */
+ skb_reserve(skb, 2);
}
- return rx;
+ if (refilled < budget)
+ mp->work_rx_refill &= ~(1 << rxq->index);
+
+oom:
+ return refilled;
}
-#endif
/* tx ***********************************************************************/
static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
{
- unsigned int frag;
- skb_frag_t *fragp;
+ int frag;
for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
- fragp = &skb_shinfo(skb)->frags[frag];
- if (fragp->size <= 8 && fragp->page_offset & 0x7)
+ skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
+ if (fragp->size <= 8 && fragp->page_offset & 7)
return 1;
}
+
return 0;
}
-static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
+static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
{
- int tx_desc_curr;
-
- BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
-
- tx_desc_curr = mp->tx_curr_desc;
- mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
-
- BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int nr_frags = skb_shinfo(skb)->nr_frags;
+ int frag;
- return tx_desc_curr;
-}
+ for (frag = 0; frag < nr_frags; frag++) {
+ skb_frag_t *this_frag;
+ int tx_index;
+ struct tx_desc *desc;
-static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
- struct sk_buff *skb)
-{
- int frag;
- int tx_index;
- struct tx_desc *desc;
+ this_frag = &skb_shinfo(skb)->frags[frag];
+ tx_index = txq->tx_curr_desc++;
+ if (txq->tx_curr_desc == txq->tx_ring_size)
+ txq->tx_curr_desc = 0;
+ desc = &txq->tx_desc_area[tx_index];
- for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
- skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
-
- tx_index = alloc_tx_desc_index(mp);
- desc = &mp->tx_desc_area[tx_index];
-
- desc->cmd_sts = BUFFER_OWNED_BY_DMA;
- /* Last Frag enables interrupt and frees the skb */
- if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
- desc->cmd_sts |= ZERO_PADDING |
- TX_LAST_DESC |
- TX_ENABLE_INTERRUPT;
- mp->tx_skb[tx_index] = skb;
- } else
- mp->tx_skb[tx_index] = NULL;
+ /*
+ * The last fragment will generate an interrupt
+ * which will free the skb on TX completion.
+ */
+ if (frag == nr_frags - 1) {
+ desc->cmd_sts = BUFFER_OWNED_BY_DMA |
+ ZERO_PADDING | TX_LAST_DESC |
+ TX_ENABLE_INTERRUPT;
+ } else {
+ desc->cmd_sts = BUFFER_OWNED_BY_DMA;
+ }
- desc = &mp->tx_desc_area[tx_index];
desc->l4i_chk = 0;
desc->byte_cnt = this_frag->size;
- desc->buf_ptr = dma_map_page(NULL, this_frag->page,
- this_frag->page_offset,
- this_frag->size,
- DMA_TO_DEVICE);
+ desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
+ this_frag->page,
+ this_frag->page_offset,
+ this_frag->size, DMA_TO_DEVICE);
}
}
return (__force __be16)sum;
}
-static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
- struct sk_buff *skb)
+static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int nr_frags = skb_shinfo(skb)->nr_frags;
int tx_index;
struct tx_desc *desc;
u32 cmd_sts;
+ u16 l4i_chk;
int length;
- int nr_frags = skb_shinfo(skb)->nr_frags;
cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
+ l4i_chk = 0;
- tx_index = alloc_tx_desc_index(mp);
- desc = &mp->tx_desc_area[tx_index];
-
- if (nr_frags) {
- tx_fill_frag_descs(mp, skb);
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ int tag_bytes;
- length = skb_headlen(skb);
- mp->tx_skb[tx_index] = NULL;
- } else {
- cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
- length = skb->len;
- mp->tx_skb[tx_index] = skb;
- }
+ BUG_ON(skb->protocol != htons(ETH_P_IP) &&
+ skb->protocol != htons(ETH_P_8021Q));
- desc->byte_cnt = length;
- desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
+ tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
+ if (unlikely(tag_bytes & ~12)) {
+ if (skb_checksum_help(skb) == 0)
+ goto no_csum;
+ kfree_skb(skb);
+ return 1;
+ }
- if (skb->ip_summed == CHECKSUM_PARTIAL) {
- BUG_ON(skb->protocol != htons(ETH_P_IP));
+ if (tag_bytes & 4)
+ cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
+ if (tag_bytes & 8)
+ cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
cmd_sts |= GEN_TCP_UDP_CHECKSUM |
GEN_IP_V4_CHECKSUM |
switch (ip_hdr(skb)->protocol) {
case IPPROTO_UDP:
cmd_sts |= UDP_FRAME;
- desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
+ l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
break;
case IPPROTO_TCP:
- desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
+ l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
break;
default:
BUG();
}
} else {
+no_csum:
/* Errata BTS #50, IHL must be 5 if no HW checksum */
cmd_sts |= 5 << TX_IHL_SHIFT;
- desc->l4i_chk = 0;
}
+ tx_index = txq->tx_curr_desc++;
+ if (txq->tx_curr_desc == txq->tx_ring_size)
+ txq->tx_curr_desc = 0;
+ desc = &txq->tx_desc_area[tx_index];
+
+ if (nr_frags) {
+ txq_submit_frag_skb(txq, skb);
+ length = skb_headlen(skb);
+ } else {
+ cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
+ length = skb->len;
+ }
+
+ desc->l4i_chk = l4i_chk;
+ desc->byte_cnt = length;
+ desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
+ length, DMA_TO_DEVICE);
+
+ __skb_queue_tail(&txq->tx_skb, skb);
+
/* ensure all other descriptors are written before first cmd_sts */
wmb();
desc->cmd_sts = cmd_sts;
+ /* clear TX_END status */
+ mp->work_tx_end &= ~(1 << txq->index);
+
/* ensure all descriptors are written before poking hardware */
wmb();
- mv643xx_eth_port_enable_tx(mp, 1);
+ txq_enable(txq);
- mp->tx_desc_count += nr_frags + 1;
+ txq->tx_desc_count += nr_frags + 1;
+
+ return 0;
}
-static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
+static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- struct net_device_stats *stats = &dev->stats;
- unsigned long flags;
+ int queue;
+ struct tx_queue *txq;
+ struct netdev_queue *nq;
- BUG_ON(netif_queue_stopped(dev));
+ queue = skb_get_queue_mapping(skb);
+ txq = mp->txq + queue;
+ nq = netdev_get_tx_queue(dev, queue);
if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
- stats->tx_dropped++;
- printk(KERN_DEBUG "%s: failed to linearize tiny "
- "unaligned fragment\n", dev->name);
+ txq->tx_dropped++;
+ dev_printk(KERN_DEBUG, &dev->dev,
+ "failed to linearize skb with tiny "
+ "unaligned fragment\n");
return NETDEV_TX_BUSY;
}
- spin_lock_irqsave(&mp->lock, flags);
-
- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
- printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
- netif_stop_queue(dev);
- spin_unlock_irqrestore(&mp->lock, flags);
- return NETDEV_TX_BUSY;
+ if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
+ if (net_ratelimit())
+ dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
+ kfree_skb(skb);
+ return NETDEV_TX_OK;
}
- tx_submit_descs_for_skb(mp, skb);
- stats->tx_bytes += skb->len;
- stats->tx_packets++;
- dev->trans_start = jiffies;
+ if (!txq_submit_skb(txq, skb)) {
+ int entries_left;
- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
- netif_stop_queue(dev);
+ txq->tx_bytes += skb->len;
+ txq->tx_packets++;
+ dev->trans_start = jiffies;
- spin_unlock_irqrestore(&mp->lock, flags);
+ entries_left = txq->tx_ring_size - txq->tx_desc_count;
+ if (entries_left < MAX_SKB_FRAGS + 1)
+ netif_tx_stop_queue(nq);
+ }
return NETDEV_TX_OK;
}
-/* mii management interface *************************************************/
-static int phy_addr_get(struct mv643xx_eth_private *mp);
-
-static void read_smi_reg(struct mv643xx_eth_private *mp,
- unsigned int phy_reg, unsigned int *value)
+/* tx napi ******************************************************************/
+static void txq_kick(struct tx_queue *txq)
{
- void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
- int phy_addr = phy_addr_get(mp);
- unsigned long flags;
- int i;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
+ u32 hw_desc_ptr;
+ u32 expected_ptr;
- /* the SMI register is a shared resource */
- spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
+ __netif_tx_lock(nq, smp_processor_id());
- /* wait for the SMI register to become available */
- for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
- if (i == 1000) {
- printk("%s: PHY busy timeout\n", mp->dev->name);
- goto out;
- }
- udelay(10);
- }
+ if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
+ goto out;
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
+ hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
+ expected_ptr = (u32)txq->tx_desc_dma +
+ txq->tx_curr_desc * sizeof(struct tx_desc);
- /* now wait for the data to be valid */
- for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
- if (i == 1000) {
- printk("%s: PHY read timeout\n", mp->dev->name);
- goto out;
- }
- udelay(10);
- }
+ if (hw_desc_ptr != expected_ptr)
+ txq_enable(txq);
- *value = readl(smi_reg) & 0xffff;
out:
- spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
+ __netif_tx_unlock(nq);
+
+ mp->work_tx_end &= ~(1 << txq->index);
}
-static void write_smi_reg(struct mv643xx_eth_private *mp,
- unsigned int phy_reg, unsigned int value)
+static int txq_reclaim(struct tx_queue *txq, int budget, int force)
{
- void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
- int phy_addr = phy_addr_get(mp);
- unsigned long flags;
- int i;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
+ int reclaimed;
- /* the SMI register is a shared resource */
- spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
+ __netif_tx_lock(nq, smp_processor_id());
- /* wait for the SMI register to become available */
- for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
- if (i == 1000) {
- printk("%s: PHY busy timeout\n", mp->dev->name);
- goto out;
+ reclaimed = 0;
+ while (reclaimed < budget && txq->tx_desc_count > 0) {
+ int tx_index;
+ struct tx_desc *desc;
+ u32 cmd_sts;
+ struct sk_buff *skb;
+
+ tx_index = txq->tx_used_desc;
+ desc = &txq->tx_desc_area[tx_index];
+ cmd_sts = desc->cmd_sts;
+
+ if (cmd_sts & BUFFER_OWNED_BY_DMA) {
+ if (!force)
+ break;
+ desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
}
- udelay(10);
- }
- writel((phy_addr << 16) | (phy_reg << 21) |
- SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
-out:
- spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
-}
+ txq->tx_used_desc = tx_index + 1;
+ if (txq->tx_used_desc == txq->tx_ring_size)
+ txq->tx_used_desc = 0;
+ reclaimed++;
+ txq->tx_desc_count--;
-/* mib counters *************************************************************/
-static void clear_mib_counters(struct mv643xx_eth_private *mp)
-{
- unsigned int port_num = mp->port_num;
- int i;
+ skb = NULL;
+ if (cmd_sts & TX_LAST_DESC)
+ skb = __skb_dequeue(&txq->tx_skb);
- /* Perform dummy reads from MIB counters */
- for (i = 0; i < 0x80; i += 4)
- rdl(mp, MIB_COUNTERS(port_num) + i);
-}
+ if (cmd_sts & ERROR_SUMMARY) {
+ dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
+ mp->dev->stats.tx_errors++;
+ }
-static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
-{
- return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
-}
+ if (cmd_sts & TX_FIRST_DESC) {
+ dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
+ desc->byte_cnt, DMA_TO_DEVICE);
+ } else {
+ dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
+ desc->byte_cnt, DMA_TO_DEVICE);
+ }
-static void update_mib_counters(struct mv643xx_eth_private *mp)
-{
- struct mib_counters *p = &mp->mib_counters;
+ if (skb != NULL) {
+ if (skb_queue_len(&mp->rx_recycle) <
+ mp->rx_ring_size &&
+ skb_recycle_check(skb, mp->skb_size +
+ dma_get_cache_alignment() - 1))
+ __skb_queue_head(&mp->rx_recycle, skb);
+ else
+ dev_kfree_skb(skb);
+ }
+ }
- p->good_octets_received += read_mib(mp, 0x00);
- p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
- p->bad_octets_received += read_mib(mp, 0x08);
- p->internal_mac_transmit_err += read_mib(mp, 0x0c);
- p->good_frames_received += read_mib(mp, 0x10);
- p->bad_frames_received += read_mib(mp, 0x14);
- p->broadcast_frames_received += read_mib(mp, 0x18);
- p->multicast_frames_received += read_mib(mp, 0x1c);
- p->frames_64_octets += read_mib(mp, 0x20);
- p->frames_65_to_127_octets += read_mib(mp, 0x24);
- p->frames_128_to_255_octets += read_mib(mp, 0x28);
- p->frames_256_to_511_octets += read_mib(mp, 0x2c);
- p->frames_512_to_1023_octets += read_mib(mp, 0x30);
- p->frames_1024_to_max_octets += read_mib(mp, 0x34);
- p->good_octets_sent += read_mib(mp, 0x38);
- p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
- p->good_frames_sent += read_mib(mp, 0x40);
- p->excessive_collision += read_mib(mp, 0x44);
- p->multicast_frames_sent += read_mib(mp, 0x48);
- p->broadcast_frames_sent += read_mib(mp, 0x4c);
- p->unrec_mac_control_received += read_mib(mp, 0x50);
- p->fc_sent += read_mib(mp, 0x54);
- p->good_fc_received += read_mib(mp, 0x58);
- p->bad_fc_received += read_mib(mp, 0x5c);
- p->undersize_received += read_mib(mp, 0x60);
- p->fragments_received += read_mib(mp, 0x64);
- p->oversize_received += read_mib(mp, 0x68);
- p->jabber_received += read_mib(mp, 0x6c);
- p->mac_receive_error += read_mib(mp, 0x70);
- p->bad_crc_event += read_mib(mp, 0x74);
- p->collision += read_mib(mp, 0x78);
- p->late_collision += read_mib(mp, 0x7c);
-}
+ __netif_tx_unlock(nq);
+
+ if (reclaimed < budget)
+ mp->work_tx &= ~(1 << txq->index);
+
+ return reclaimed;
+}
+
+
+/* tx rate control **********************************************************/
+/*
+ * Set total maximum TX rate (shared by all TX queues for this port)
+ * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
+ */
+static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
+{
+ int token_rate;
+ int mtu;
+ int bucket_size;
+
+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
+ if (token_rate > 1023)
+ token_rate = 1023;
+
+ mtu = (mp->dev->mtu + 255) >> 8;
+ if (mtu > 63)
+ mtu = 63;
+
+ bucket_size = (burst + 255) >> 8;
+ if (bucket_size > 65535)
+ bucket_size = 65535;
+
+ switch (mp->shared->tx_bw_control) {
+ case TX_BW_CONTROL_OLD_LAYOUT:
+ wrlp(mp, TX_BW_RATE, token_rate);
+ wrlp(mp, TX_BW_MTU, mtu);
+ wrlp(mp, TX_BW_BURST, bucket_size);
+ break;
+ case TX_BW_CONTROL_NEW_LAYOUT:
+ wrlp(mp, TX_BW_RATE_MOVED, token_rate);
+ wrlp(mp, TX_BW_MTU_MOVED, mtu);
+ wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
+ break;
+ }
+}
+
+static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int token_rate;
+ int bucket_size;
+
+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
+ if (token_rate > 1023)
+ token_rate = 1023;
+
+ bucket_size = (burst + 255) >> 8;
+ if (bucket_size > 65535)
+ bucket_size = 65535;
+
+ wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
+ wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
+}
+
+static void txq_set_fixed_prio_mode(struct tx_queue *txq)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int off;
+ u32 val;
+
+ /*
+ * Turn on fixed priority mode.
+ */
+ off = 0;
+ switch (mp->shared->tx_bw_control) {
+ case TX_BW_CONTROL_OLD_LAYOUT:
+ off = TXQ_FIX_PRIO_CONF;
+ break;
+ case TX_BW_CONTROL_NEW_LAYOUT:
+ off = TXQ_FIX_PRIO_CONF_MOVED;
+ break;
+ }
+
+ if (off) {
+ val = rdlp(mp, off);
+ val |= 1 << txq->index;
+ wrlp(mp, off, val);
+ }
+}
+
+static void txq_set_wrr(struct tx_queue *txq, int weight)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int off;
+ u32 val;
+
+ /*
+ * Turn off fixed priority mode.
+ */
+ off = 0;
+ switch (mp->shared->tx_bw_control) {
+ case TX_BW_CONTROL_OLD_LAYOUT:
+ off = TXQ_FIX_PRIO_CONF;
+ break;
+ case TX_BW_CONTROL_NEW_LAYOUT:
+ off = TXQ_FIX_PRIO_CONF_MOVED;
+ break;
+ }
+
+ if (off) {
+ val = rdlp(mp, off);
+ val &= ~(1 << txq->index);
+ wrlp(mp, off, val);
+
+ /*
+ * Configure WRR weight for this queue.
+ */
+
+ val = rdlp(mp, off);
+ val = (val & ~0xff) | (weight & 0xff);
+ wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
+ }
+}
+
+
+/* mii management interface *************************************************/
+static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
+{
+ struct mv643xx_eth_shared_private *msp = dev_id;
+
+ if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
+ writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
+ wake_up(&msp->smi_busy_wait);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static int smi_is_done(struct mv643xx_eth_shared_private *msp)
+{
+ return !(readl(msp->base + SMI_REG) & SMI_BUSY);
+}
+
+static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
+{
+ if (msp->err_interrupt == NO_IRQ) {
+ int i;
+
+ for (i = 0; !smi_is_done(msp); i++) {
+ if (i == 10)
+ return -ETIMEDOUT;
+ msleep(10);
+ }
+
+ return 0;
+ }
+
+ if (!smi_is_done(msp)) {
+ wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
+ msecs_to_jiffies(100));
+ if (!smi_is_done(msp))
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
+{
+ struct mv643xx_eth_shared_private *msp = bus->priv;
+ void __iomem *smi_reg = msp->base + SMI_REG;
+ int ret;
+
+ if (smi_wait_ready(msp)) {
+ printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
+
+ if (smi_wait_ready(msp)) {
+ printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ ret = readl(smi_reg);
+ if (!(ret & SMI_READ_VALID)) {
+ printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
+ return -ENODEV;
+ }
+
+ return ret & 0xffff;
+}
+
+static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
+{
+ struct mv643xx_eth_shared_private *msp = bus->priv;
+ void __iomem *smi_reg = msp->base + SMI_REG;
+
+ if (smi_wait_ready(msp)) {
+ printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(SMI_OPCODE_WRITE | (reg << 21) |
+ (addr << 16) | (val & 0xffff), smi_reg);
+
+ if (smi_wait_ready(msp)) {
+ printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+
+/* statistics ***************************************************************/
+static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+ unsigned long tx_packets = 0;
+ unsigned long tx_bytes = 0;
+ unsigned long tx_dropped = 0;
+ int i;
+
+ for (i = 0; i < mp->txq_count; i++) {
+ struct tx_queue *txq = mp->txq + i;
+
+ tx_packets += txq->tx_packets;
+ tx_bytes += txq->tx_bytes;
+ tx_dropped += txq->tx_dropped;
+ }
+
+ stats->tx_packets = tx_packets;
+ stats->tx_bytes = tx_bytes;
+ stats->tx_dropped = tx_dropped;
+
+ return stats;
+}
+
+static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
+{
+ u32 lro_aggregated = 0;
+ u32 lro_flushed = 0;
+ u32 lro_no_desc = 0;
+ int i;
+
+ for (i = 0; i < mp->rxq_count; i++) {
+ struct rx_queue *rxq = mp->rxq + i;
+
+ lro_aggregated += rxq->lro_mgr.stats.aggregated;
+ lro_flushed += rxq->lro_mgr.stats.flushed;
+ lro_no_desc += rxq->lro_mgr.stats.no_desc;
+ }
+
+ mp->lro_counters.lro_aggregated = lro_aggregated;
+ mp->lro_counters.lro_flushed = lro_flushed;
+ mp->lro_counters.lro_no_desc = lro_no_desc;
+}
+
+static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
+{
+ return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
+}
+
+static void mib_counters_clear(struct mv643xx_eth_private *mp)
+{
+ int i;
+
+ for (i = 0; i < 0x80; i += 4)
+ mib_read(mp, i);
+}
+
+static void mib_counters_update(struct mv643xx_eth_private *mp)
+{
+ struct mib_counters *p = &mp->mib_counters;
+
+ spin_lock_bh(&mp->mib_counters_lock);
+ p->good_octets_received += mib_read(mp, 0x00);
+ p->bad_octets_received += mib_read(mp, 0x08);
+ p->internal_mac_transmit_err += mib_read(mp, 0x0c);
+ p->good_frames_received += mib_read(mp, 0x10);
+ p->bad_frames_received += mib_read(mp, 0x14);
+ p->broadcast_frames_received += mib_read(mp, 0x18);
+ p->multicast_frames_received += mib_read(mp, 0x1c);
+ p->frames_64_octets += mib_read(mp, 0x20);
+ p->frames_65_to_127_octets += mib_read(mp, 0x24);
+ p->frames_128_to_255_octets += mib_read(mp, 0x28);
+ p->frames_256_to_511_octets += mib_read(mp, 0x2c);
+ p->frames_512_to_1023_octets += mib_read(mp, 0x30);
+ p->frames_1024_to_max_octets += mib_read(mp, 0x34);
+ p->good_octets_sent += mib_read(mp, 0x38);
+ p->good_frames_sent += mib_read(mp, 0x40);
+ p->excessive_collision += mib_read(mp, 0x44);
+ p->multicast_frames_sent += mib_read(mp, 0x48);
+ p->broadcast_frames_sent += mib_read(mp, 0x4c);
+ p->unrec_mac_control_received += mib_read(mp, 0x50);
+ p->fc_sent += mib_read(mp, 0x54);
+ p->good_fc_received += mib_read(mp, 0x58);
+ p->bad_fc_received += mib_read(mp, 0x5c);
+ p->undersize_received += mib_read(mp, 0x60);
+ p->fragments_received += mib_read(mp, 0x64);
+ p->oversize_received += mib_read(mp, 0x68);
+ p->jabber_received += mib_read(mp, 0x6c);
+ p->mac_receive_error += mib_read(mp, 0x70);
+ p->bad_crc_event += mib_read(mp, 0x74);
+ p->collision += mib_read(mp, 0x78);
+ p->late_collision += mib_read(mp, 0x7c);
+ spin_unlock_bh(&mp->mib_counters_lock);
+
+ mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
+}
+
+static void mib_counters_timer_wrapper(unsigned long _mp)
+{
+ struct mv643xx_eth_private *mp = (void *)_mp;
+
+ mib_counters_update(mp);
+}
+
+
+/* interrupt coalescing *****************************************************/
+/*
+ * Hardware coalescing parameters are set in units of 64 t_clk
+ * cycles. I.e.:
+ *
+ * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
+ *
+ * register_value = coal_delay_in_usec * t_clk_rate / 64000000
+ *
+ * In the ->set*() methods, we round the computed register value
+ * to the nearest integer.
+ */
+static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
+{
+ u32 val = rdlp(mp, SDMA_CONFIG);
+ u64 temp;
+
+ if (mp->shared->extended_rx_coal_limit)
+ temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
+ else
+ temp = (val & 0x003fff00) >> 8;
+
+ temp *= 64000000;
+ do_div(temp, mp->shared->t_clk);
+
+ return (unsigned int)temp;
+}
+
+static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
+{
+ u64 temp;
+ u32 val;
+
+ temp = (u64)usec * mp->shared->t_clk;
+ temp += 31999999;
+ do_div(temp, 64000000);
+
+ val = rdlp(mp, SDMA_CONFIG);
+ if (mp->shared->extended_rx_coal_limit) {
+ if (temp > 0xffff)
+ temp = 0xffff;
+ val &= ~0x023fff80;
+ val |= (temp & 0x8000) << 10;
+ val |= (temp & 0x7fff) << 7;
+ } else {
+ if (temp > 0x3fff)
+ temp = 0x3fff;
+ val &= ~0x003fff00;
+ val |= (temp & 0x3fff) << 8;
+ }
+ wrlp(mp, SDMA_CONFIG, val);
+}
+
+static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
+{
+ u64 temp;
+
+ temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
+ temp *= 64000000;
+ do_div(temp, mp->shared->t_clk);
+
+ return (unsigned int)temp;
+}
+
+static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
+{
+ u64 temp;
+
+ temp = (u64)usec * mp->shared->t_clk;
+ temp += 31999999;
+ do_div(temp, 64000000);
+
+ if (temp > 0x3fff)
+ temp = 0x3fff;
+
+ wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
+}
/* ethtool ******************************************************************/
{ #m, FIELD_SIZEOF(struct mib_counters, m), \
-1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
+#define LROSTAT(m) \
+ { #m, FIELD_SIZEOF(struct lro_counters, m), \
+ -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
+
static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
SSTAT(rx_packets),
SSTAT(tx_packets),
MIBSTAT(bad_crc_event),
MIBSTAT(collision),
MIBSTAT(late_collision),
+ LROSTAT(lro_aggregated),
+ LROSTAT(lro_flushed),
+ LROSTAT(lro_no_desc),
};
-static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+static int
+mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
+ struct ethtool_cmd *cmd)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
int err;
- spin_lock_irq(&mp->lock);
- err = mii_ethtool_gset(&mp->mii, cmd);
- spin_unlock_irq(&mp->lock);
+ err = phy_read_status(mp->phy);
+ if (err == 0)
+ err = phy_ethtool_gset(mp->phy, cmd);
- /* The PHY may support 1000baseT_Half, but the mv643xx does not */
+ /*
+ * The MAC does not support 1000baseT_Half.
+ */
cmd->supported &= ~SUPPORTED_1000baseT_Half;
cmd->advertising &= ~ADVERTISED_1000baseT_Half;
return err;
}
-static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+static int
+mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
+ struct ethtool_cmd *cmd)
+{
+ u32 port_status;
+
+ port_status = rdlp(mp, PORT_STATUS);
+
+ cmd->supported = SUPPORTED_MII;
+ cmd->advertising = ADVERTISED_MII;
+ switch (port_status & PORT_SPEED_MASK) {
+ case PORT_SPEED_10:
+ cmd->speed = SPEED_10;
+ break;
+ case PORT_SPEED_100:
+ cmd->speed = SPEED_100;
+ break;
+ case PORT_SPEED_1000:
+ cmd->speed = SPEED_1000;
+ break;
+ default:
+ cmd->speed = -1;
+ break;
+ }
+ cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
+ cmd->port = PORT_MII;
+ cmd->phy_address = 0;
+ cmd->transceiver = XCVR_INTERNAL;
+ cmd->autoneg = AUTONEG_DISABLE;
+ cmd->maxtxpkt = 1;
+ cmd->maxrxpkt = 1;
+
+ return 0;
+}
+
+static int
+mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- int err;
- spin_lock_irq(&mp->lock);
- err = mii_ethtool_sset(&mp->mii, cmd);
- spin_unlock_irq(&mp->lock);
+ if (mp->phy != NULL)
+ return mv643xx_eth_get_settings_phy(mp, cmd);
+ else
+ return mv643xx_eth_get_settings_phyless(mp, cmd);
+}
- return err;
+static int
+mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ if (mp->phy == NULL)
+ return -EINVAL;
+
+ /*
+ * The MAC does not support 1000baseT_Half.
+ */
+ cmd->advertising &= ~ADVERTISED_1000baseT_Half;
+
+ return phy_ethtool_sset(mp->phy, cmd);
}
-static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
- struct ethtool_drvinfo *drvinfo)
+static void mv643xx_eth_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *drvinfo)
{
strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
strncpy(drvinfo->fw_version, "N/A", 32);
- strncpy(drvinfo->bus_info, "mv643xx", 32);
+ strncpy(drvinfo->bus_info, "platform", 32);
drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
}
-static int mv643xx_eth_nway_restart(struct net_device *dev)
+static int mv643xx_eth_nway_reset(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- return mii_nway_restart(&mp->mii);
+ if (mp->phy == NULL)
+ return -EINVAL;
+
+ return genphy_restart_aneg(mp->phy);
}
static u32 mv643xx_eth_get_link(struct net_device *dev)
{
+ return !!netif_carrier_ok(dev);
+}
+
+static int
+mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ ec->rx_coalesce_usecs = get_rx_coal(mp);
+ ec->tx_coalesce_usecs = get_tx_coal(mp);
+
+ return 0;
+}
+
+static int
+mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ set_rx_coal(mp, ec->rx_coalesce_usecs);
+ set_tx_coal(mp, ec->tx_coalesce_usecs);
+
+ return 0;
+}
+
+static void
+mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ er->rx_max_pending = 4096;
+ er->tx_max_pending = 4096;
+ er->rx_mini_max_pending = 0;
+ er->rx_jumbo_max_pending = 0;
+
+ er->rx_pending = mp->rx_ring_size;
+ er->tx_pending = mp->tx_ring_size;
+ er->rx_mini_pending = 0;
+ er->rx_jumbo_pending = 0;
+}
+
+static int
+mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ if (er->rx_mini_pending || er->rx_jumbo_pending)
+ return -EINVAL;
+
+ mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
+ mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
+
+ if (netif_running(dev)) {
+ mv643xx_eth_stop(dev);
+ if (mv643xx_eth_open(dev)) {
+ dev_printk(KERN_ERR, &dev->dev,
+ "fatal error on re-opening device after "
+ "ring param change\n");
+ return -ENOMEM;
+ }
+ }
+
+ return 0;
+}
+
+static u32
+mv643xx_eth_get_rx_csum(struct net_device *dev)
+{
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
+}
+
+static int
+mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
+{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- return mii_link_ok(&mp->mii);
+ wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
+
+ return 0;
}
-static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
- uint8_t *data)
+static void mv643xx_eth_get_strings(struct net_device *dev,
+ uint32_t stringset, uint8_t *data)
{
int i;
- switch(stringset) {
- case ETH_SS_STATS:
- for (i=0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
+ if (stringset == ETH_SS_STATS) {
+ for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
memcpy(data + i * ETH_GSTRING_LEN,
mv643xx_eth_stats[i].stat_string,
ETH_GSTRING_LEN);
}
- break;
}
}
-static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
- struct ethtool_stats *stats, uint64_t *data)
+static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats,
+ uint64_t *data)
{
- struct mv643xx_eth_private *mp = netdev->priv;
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
int i;
- update_mib_counters(mp);
+ mv643xx_eth_get_stats(dev);
+ mib_counters_update(mp);
+ mv643xx_eth_grab_lro_stats(mp);
for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
const struct mv643xx_eth_stats *stat;
}
}
-static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
+static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
{
- switch (sset) {
- case ETH_SS_STATS:
+ if (sset == ETH_SS_STATS)
return ARRAY_SIZE(mv643xx_eth_stats);
- default:
- return -EOPNOTSUPP;
- }
+
+ return -EOPNOTSUPP;
}
static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
- .get_settings = mv643xx_eth_get_settings,
- .set_settings = mv643xx_eth_set_settings,
- .get_drvinfo = mv643xx_eth_get_drvinfo,
- .get_link = mv643xx_eth_get_link,
+ .get_settings = mv643xx_eth_get_settings,
+ .set_settings = mv643xx_eth_set_settings,
+ .get_drvinfo = mv643xx_eth_get_drvinfo,
+ .nway_reset = mv643xx_eth_nway_reset,
+ .get_link = mv643xx_eth_get_link,
+ .get_coalesce = mv643xx_eth_get_coalesce,
+ .set_coalesce = mv643xx_eth_set_coalesce,
+ .get_ringparam = mv643xx_eth_get_ringparam,
+ .set_ringparam = mv643xx_eth_set_ringparam,
+ .get_rx_csum = mv643xx_eth_get_rx_csum,
+ .set_rx_csum = mv643xx_eth_set_rx_csum,
+ .set_tx_csum = ethtool_op_set_tx_csum,
.set_sg = ethtool_op_set_sg,
+ .get_strings = mv643xx_eth_get_strings,
+ .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
+ .get_flags = ethtool_op_get_flags,
+ .set_flags = ethtool_op_set_flags,
.get_sset_count = mv643xx_eth_get_sset_count,
- .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
- .get_strings = mv643xx_eth_get_strings,
- .nway_reset = mv643xx_eth_nway_restart,
};
/* address handling *********************************************************/
static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
{
- unsigned int port_num = mp->port_num;
- unsigned int mac_h;
- unsigned int mac_l;
-
- mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
- mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
+ unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
+ unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
addr[0] = (mac_h >> 24) & 0xff;
addr[1] = (mac_h >> 16) & 0xff;
addr[5] = mac_l & 0xff;
}
-static void init_mac_tables(struct mv643xx_eth_private *mp)
+static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
{
- unsigned int port_num = mp->port_num;
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
-
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
- }
+ wrlp(mp, MAC_ADDR_HIGH,
+ (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
+ wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
}
-static void set_filter_table_entry(struct mv643xx_eth_private *mp,
- int table, unsigned char entry)
+static u32 uc_addr_filter_mask(struct net_device *dev)
{
- unsigned int table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
- reg_offset = entry % 4; /* Entry offset within the register */
+ struct dev_addr_list *uc_ptr;
+ u32 nibbles;
- /* Set "accepts frame bit" at specified table entry */
- table_reg = rdl(mp, table + tbl_offset);
- table_reg |= 0x01 << (8 * reg_offset);
- wrl(mp, table + tbl_offset, table_reg);
-}
-
-static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
-{
- unsigned int port_num = mp->port_num;
- unsigned int mac_h;
- unsigned int mac_l;
- int table;
+ if (dev->flags & IFF_PROMISC)
+ return 0;
- mac_l = (addr[4] << 8) | (addr[5]);
- mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
- (addr[3] << 0);
+ nibbles = 1 << (dev->dev_addr[5] & 0x0f);
+ for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
+ if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
+ return 0;
+ if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
+ return 0;
- wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
- wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
+ nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
+ }
- /* Accept frames with this address */
- table = UNICAST_TABLE(port_num);
- set_filter_table_entry(mp, table, addr[5] & 0x0f);
+ return nibbles;
}
-static void mv643xx_eth_update_mac_address(struct net_device *dev)
+static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
+ u32 port_config;
+ u32 nibbles;
+ int i;
- init_mac_tables(mp);
uc_addr_set(mp, dev->dev_addr);
-}
-static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
-{
- int i;
+ port_config = rdlp(mp, PORT_CONFIG);
+ nibbles = uc_addr_filter_mask(dev);
+ if (!nibbles) {
+ port_config |= UNICAST_PROMISCUOUS_MODE;
+ wrlp(mp, PORT_CONFIG, port_config);
+ return;
+ }
- for (i = 0; i < 6; i++)
- /* +2 is for the offset of the HW addr type */
- dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
- mv643xx_eth_update_mac_address(dev);
- return 0;
+ for (i = 0; i < 16; i += 4) {
+ int off = UNICAST_TABLE(mp->port_num) + i;
+ u32 v;
+
+ v = 0;
+ if (nibbles & 1)
+ v |= 0x00000001;
+ if (nibbles & 2)
+ v |= 0x00000100;
+ if (nibbles & 4)
+ v |= 0x00010000;
+ if (nibbles & 8)
+ v |= 0x01000000;
+ nibbles >>= 4;
+
+ wrl(mp, off, v);
+ }
+
+ port_config &= ~UNICAST_PROMISCUOUS_MODE;
+ wrlp(mp, PORT_CONFIG, port_config);
}
static int addr_crc(unsigned char *addr)
return crc;
}
-static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
+static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
{
- unsigned int port_num = mp->port_num;
- int table;
- int crc;
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+ u32 *mc_spec;
+ u32 *mc_other;
+ struct dev_addr_list *addr;
+ int i;
- if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
- (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
- table = SPECIAL_MCAST_TABLE(port_num);
- set_filter_table_entry(mp, table, addr[5]);
+ if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
+ int port_num;
+ u32 accept;
+ int i;
+
+oom:
+ port_num = mp->port_num;
+ accept = 0x01010101;
+ for (i = 0; i < 0x100; i += 4) {
+ wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
+ wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
+ }
return;
}
- crc = addr_crc(addr);
+ mc_spec = kmalloc(0x200, GFP_ATOMIC);
+ if (mc_spec == NULL)
+ goto oom;
+ mc_other = mc_spec + (0x100 >> 2);
- table = OTHER_MCAST_TABLE(port_num);
- set_filter_table_entry(mp, table, crc);
-}
-
-static void set_multicast_list(struct net_device *dev)
-{
+ memset(mc_spec, 0, 0x100);
+ memset(mc_other, 0, 0x100);
- struct dev_mc_list *mc_list;
- int i;
- int table_index;
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
+ u8 *a = addr->da_addr;
+ u32 *table;
+ int entry;
- /* If the device is in promiscuous mode or in all multicast mode,
- * we will fully populate both multicast tables with accept.
- * This is guaranteed to yield a match on all multicast addresses...
- */
- if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Set all entries in DA filter special multicast
- * table (Ex_dFSMT)
- * Set for ETH_Q0 for now
- * Bits
- * 0 Accept=1, Drop=0
- * 3-1 Queue ETH_Q0=0
- * 7-4 Reserved = 0;
- */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
-
- /* Set all entries in DA filter other multicast
- * table (Ex_dFOMT)
- * Set for ETH_Q0 for now
- * Bits
- * 0 Accept=1, Drop=0
- * 3-1 Queue ETH_Q0=0
- * 7-4 Reserved = 0;
- */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
+ if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
+ table = mc_spec;
+ entry = a[5];
+ } else {
+ table = mc_other;
+ entry = addr_crc(a);
}
- return;
- }
- /* We will clear out multicast tables every time we get the list.
- * Then add the entire new list...
- */
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
+ table[entry >> 2] |= 1 << (8 * (entry & 3));
+ }
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
+ for (i = 0; i < 0x100; i += 4) {
+ wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
+ wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
}
- /* Get pointer to net_device multicast list and add each one... */
- for (i = 0, mc_list = dev->mc_list;
- (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
- i++, mc_list = mc_list->next)
- if (mc_list->dmi_addrlen == 6)
- mc_addr(mp, mc_list->dmi_addr);
+ kfree(mc_spec);
}
static void mv643xx_eth_set_rx_mode(struct net_device *dev)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- u32 config_reg;
+ mv643xx_eth_program_unicast_filter(dev);
+ mv643xx_eth_program_multicast_filter(dev);
+}
- config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
- if (dev->flags & IFF_PROMISC)
- config_reg |= UNICAST_PROMISCUOUS_MODE;
- else
- config_reg &= ~UNICAST_PROMISCUOUS_MODE;
- wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
+static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
+{
+ struct sockaddr *sa = addr;
+
+ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
+
+ netif_addr_lock_bh(dev);
+ mv643xx_eth_program_unicast_filter(dev);
+ netif_addr_unlock_bh(dev);
- set_multicast_list(dev);
+ return 0;
}
/* rx/tx queue initialisation ***********************************************/
-static int rxq_init(struct mv643xx_eth_private *mp)
+static int rxq_init(struct mv643xx_eth_private *mp, int index)
{
- struct rx_queue *rxq = mp->rxq;
+ struct rx_queue *rxq = mp->rxq + index;
struct rx_desc *rx_desc;
int size;
int i;
- rxq->rx_ring_size = mp->default_rx_ring_size;
+ rxq->index = index;
+
+ rxq->rx_ring_size = mp->rx_ring_size;
rxq->rx_desc_count = 0;
rxq->rx_curr_desc = 0;
size = rxq->rx_ring_size * sizeof(struct rx_desc);
- if (size <= mp->rx_desc_sram_size) {
+ if (index == 0 && size <= mp->rx_desc_sram_size) {
rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
mp->rx_desc_sram_size);
rxq->rx_desc_dma = mp->rx_desc_sram_addr;
} else {
- rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
- &rxq->rx_desc_dma,
- GFP_KERNEL);
+ rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
+ size, &rxq->rx_desc_dma,
+ GFP_KERNEL);
}
if (rxq->rx_desc_area == NULL) {
rx_desc = (struct rx_desc *)rxq->rx_desc_area;
for (i = 0; i < rxq->rx_ring_size; i++) {
- int nexti = (i + 1) % rxq->rx_ring_size;
+ int nexti;
+
+ nexti = i + 1;
+ if (nexti == rxq->rx_ring_size)
+ nexti = 0;
+
rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
nexti * sizeof(struct rx_desc);
}
- init_timer(&rxq->rx_oom);
- rxq->rx_oom.data = (unsigned long)rxq;
- rxq->rx_oom.function = rxq_refill_timer_wrapper;
+ rxq->lro_mgr.dev = mp->dev;
+ memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
+ rxq->lro_mgr.features = LRO_F_NAPI;
+ rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
+ rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
+ rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
+ rxq->lro_mgr.max_aggr = 32;
+ rxq->lro_mgr.frag_align_pad = 0;
+ rxq->lro_mgr.lro_arr = rxq->lro_arr;
+ rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
+
+ memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
return 0;
out_free:
- if (size <= mp->rx_desc_sram_size)
+ if (index == 0 && size <= mp->rx_desc_sram_size)
iounmap(rxq->rx_desc_area);
else
- dma_free_coherent(NULL, size,
+ dma_free_coherent(mp->dev->dev.parent, size,
rxq->rx_desc_area,
rxq->rx_desc_dma);
rxq_disable(rxq);
- del_timer_sync(&rxq->rx_oom);
-
for (i = 0; i < rxq->rx_ring_size; i++) {
if (rxq->rx_skb[i]) {
dev_kfree_skb(rxq->rx_skb[i]);
rxq->rx_desc_count);
}
- if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
+ if (rxq->index == 0 &&
+ rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
iounmap(rxq->rx_desc_area);
else
- dma_free_coherent(NULL, rxq->rx_desc_area_size,
+ dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
rxq->rx_desc_area, rxq->rx_desc_dma);
kfree(rxq->rx_skb);
}
-static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
+static int txq_init(struct mv643xx_eth_private *mp, int index)
{
- int tx_desc_num = mp->tx_ring_size;
- struct tx_desc *p_tx_desc;
+ struct tx_queue *txq = mp->txq + index;
+ struct tx_desc *tx_desc;
+ int size;
int i;
- /* Initialize the next_desc_ptr links in the Tx descriptors ring */
- p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
- for (i = 0; i < tx_desc_num; i++) {
- p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
- ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
- }
+ txq->index = index;
- mp->tx_curr_desc = 0;
- mp->tx_used_desc = 0;
+ txq->tx_ring_size = mp->tx_ring_size;
- mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
-}
+ txq->tx_desc_count = 0;
+ txq->tx_curr_desc = 0;
+ txq->tx_used_desc = 0;
-static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- struct tx_desc *desc;
- u32 cmd_sts;
- struct sk_buff *skb;
- unsigned long flags;
- int tx_index;
- dma_addr_t addr;
- int count;
- int released = 0;
+ size = txq->tx_ring_size * sizeof(struct tx_desc);
- while (mp->tx_desc_count > 0) {
- spin_lock_irqsave(&mp->lock, flags);
+ if (index == 0 && size <= mp->tx_desc_sram_size) {
+ txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
+ mp->tx_desc_sram_size);
+ txq->tx_desc_dma = mp->tx_desc_sram_addr;
+ } else {
+ txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
+ size, &txq->tx_desc_dma,
+ GFP_KERNEL);
+ }
- /* tx_desc_count might have changed before acquiring the lock */
- if (mp->tx_desc_count <= 0) {
- spin_unlock_irqrestore(&mp->lock, flags);
- return released;
- }
+ if (txq->tx_desc_area == NULL) {
+ dev_printk(KERN_ERR, &mp->dev->dev,
+ "can't allocate tx ring (%d bytes)\n", size);
+ return -ENOMEM;
+ }
+ memset(txq->tx_desc_area, 0, size);
- tx_index = mp->tx_used_desc;
- desc = &mp->tx_desc_area[tx_index];
- cmd_sts = desc->cmd_sts;
+ txq->tx_desc_area_size = size;
- if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
- spin_unlock_irqrestore(&mp->lock, flags);
- return released;
- }
+ tx_desc = (struct tx_desc *)txq->tx_desc_area;
+ for (i = 0; i < txq->tx_ring_size; i++) {
+ struct tx_desc *txd = tx_desc + i;
+ int nexti;
- mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
- mp->tx_desc_count--;
+ nexti = i + 1;
+ if (nexti == txq->tx_ring_size)
+ nexti = 0;
- addr = desc->buf_ptr;
- count = desc->byte_cnt;
- skb = mp->tx_skb[tx_index];
- if (skb)
- mp->tx_skb[tx_index] = NULL;
+ txd->cmd_sts = 0;
+ txd->next_desc_ptr = txq->tx_desc_dma +
+ nexti * sizeof(struct tx_desc);
+ }
- if (cmd_sts & ERROR_SUMMARY) {
- printk("%s: Error in TX\n", dev->name);
- dev->stats.tx_errors++;
- }
+ skb_queue_head_init(&txq->tx_skb);
- spin_unlock_irqrestore(&mp->lock, flags);
+ return 0;
+}
- if (cmd_sts & TX_FIRST_DESC)
- dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
- else
- dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
+static void txq_deinit(struct tx_queue *txq)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
- if (skb)
- dev_kfree_skb_irq(skb);
+ txq_disable(txq);
+ txq_reclaim(txq, txq->tx_ring_size, 1);
- released = 1;
- }
+ BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
- return released;
+ if (txq->index == 0 &&
+ txq->tx_desc_area_size <= mp->tx_desc_sram_size)
+ iounmap(txq->tx_desc_area);
+ else
+ dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
+ txq->tx_desc_area, txq->tx_desc_dma);
}
-static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
+
+/* netdev ops and related ***************************************************/
+static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
+ u32 int_cause;
+ u32 int_cause_ext;
- if (mv643xx_eth_free_tx_descs(dev, 0) &&
- mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
-}
+ int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
+ if (int_cause == 0)
+ return 0;
-static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
-{
- mv643xx_eth_free_tx_descs(dev, 1);
+ int_cause_ext = 0;
+ if (int_cause & INT_EXT)
+ int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
+
+ int_cause &= INT_TX_END | INT_RX;
+ if (int_cause) {
+ wrlp(mp, INT_CAUSE, ~int_cause);
+ mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
+ ~(rdlp(mp, TXQ_COMMAND) & 0xff);
+ mp->work_rx |= (int_cause & INT_RX) >> 2;
+ }
+
+ int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
+ if (int_cause_ext) {
+ wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
+ if (int_cause_ext & INT_EXT_LINK_PHY)
+ mp->work_link = 1;
+ mp->work_tx |= int_cause_ext & INT_EXT_TX;
+ }
+
+ return 1;
}
-static void mv643xx_eth_free_tx_rings(struct net_device *dev)
+static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
{
+ struct net_device *dev = (struct net_device *)dev_id;
struct mv643xx_eth_private *mp = netdev_priv(dev);
- /* Stop Tx Queues */
- mv643xx_eth_port_disable_tx(mp);
-
- /* Free outstanding skb's on TX ring */
- mv643xx_eth_free_all_tx_descs(dev);
+ if (unlikely(!mv643xx_eth_collect_events(mp)))
+ return IRQ_NONE;
- BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
+ wrlp(mp, INT_MASK, 0);
+ napi_schedule(&mp->napi);
- /* Free TX ring */
- if (mp->tx_sram_size)
- iounmap(mp->tx_desc_area);
- else
- dma_free_coherent(NULL, mp->tx_desc_area_size,
- mp->tx_desc_area, mp->tx_desc_dma);
+ return IRQ_HANDLED;
}
+static void handle_link_event(struct mv643xx_eth_private *mp)
+{
+ struct net_device *dev = mp->dev;
+ u32 port_status;
+ int speed;
+ int duplex;
+ int fc;
-/* netdev ops and related ***************************************************/
-static void port_reset(struct mv643xx_eth_private *mp);
+ port_status = rdlp(mp, PORT_STATUS);
+ if (!(port_status & LINK_UP)) {
+ if (netif_carrier_ok(dev)) {
+ int i;
-static void mv643xx_eth_update_pscr(struct net_device *dev,
- struct ethtool_cmd *ecmd)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- int port_num = mp->port_num;
- u32 o_pscr, n_pscr;
- unsigned int queues;
-
- o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
- n_pscr = o_pscr;
-
- /* clear speed, duplex and rx buffer size fields */
- n_pscr &= ~(SET_MII_SPEED_TO_100 |
- SET_GMII_SPEED_TO_1000 |
- SET_FULL_DUPLEX_MODE |
- MAX_RX_PACKET_MASK);
-
- if (ecmd->duplex == DUPLEX_FULL)
- n_pscr |= SET_FULL_DUPLEX_MODE;
-
- if (ecmd->speed == SPEED_1000)
- n_pscr |= SET_GMII_SPEED_TO_1000 |
- MAX_RX_PACKET_9700BYTE;
- else {
- if (ecmd->speed == SPEED_100)
- n_pscr |= SET_MII_SPEED_TO_100;
- n_pscr |= MAX_RX_PACKET_1522BYTE;
- }
-
- if (n_pscr != o_pscr) {
- if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
- else {
- queues = mv643xx_eth_port_disable_tx(mp);
-
- o_pscr &= ~SERIAL_PORT_ENABLE;
- wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
- if (queues)
- mv643xx_eth_port_enable_tx(mp, queues);
+ printk(KERN_INFO "%s: link down\n", dev->name);
+
+ netif_carrier_off(dev);
+
+ for (i = 0; i < mp->txq_count; i++) {
+ struct tx_queue *txq = mp->txq + i;
+
+ txq_reclaim(txq, txq->tx_ring_size, 1);
+ txq_reset_hw_ptr(txq);
+ }
}
+ return;
+ }
+
+ switch (port_status & PORT_SPEED_MASK) {
+ case PORT_SPEED_10:
+ speed = 10;
+ break;
+ case PORT_SPEED_100:
+ speed = 100;
+ break;
+ case PORT_SPEED_1000:
+ speed = 1000;
+ break;
+ default:
+ speed = -1;
+ break;
}
+ duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
+ fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
+
+ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
+ "flow control %sabled\n", dev->name,
+ speed, duplex ? "full" : "half",
+ fc ? "en" : "dis");
+
+ if (!netif_carrier_ok(dev))
+ netif_carrier_on(dev);
}
-static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
+static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
{
- struct net_device *dev = (struct net_device *)dev_id;
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- u32 int_cause, int_cause_ext = 0;
- unsigned int port_num = mp->port_num;
+ struct mv643xx_eth_private *mp;
+ int work_done;
- /* Read interrupt cause registers */
- int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
- if (int_cause & INT_EXT) {
- int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
- & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
- wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
+ mp = container_of(napi, struct mv643xx_eth_private, napi);
+
+ if (unlikely(mp->oom)) {
+ mp->oom = 0;
+ del_timer(&mp->rx_oom);
}
- /* PHY status changed */
- if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
- struct ethtool_cmd cmd;
+ work_done = 0;
+ while (work_done < budget) {
+ u8 queue_mask;
+ int queue;
+ int work_tbd;
- if (mii_link_ok(&mp->mii)) {
- mii_ethtool_gset(&mp->mii, &cmd);
- mv643xx_eth_update_pscr(dev, &cmd);
- mv643xx_eth_port_enable_tx(mp, 1);
- if (!netif_carrier_ok(dev)) {
- netif_carrier_on(dev);
- if (mp->tx_ring_size - mp->tx_desc_count >=
- MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
- }
- } else if (netif_carrier_ok(dev)) {
- netif_stop_queue(dev);
- netif_carrier_off(dev);
+ if (mp->work_link) {
+ mp->work_link = 0;
+ handle_link_event(mp);
+ continue;
}
- }
-#ifdef MV643XX_ETH_NAPI
- if (int_cause & INT_RX) {
- /* schedule the NAPI poll routine to maintain port */
- wrl(mp, INT_MASK(port_num), 0x00000000);
+ queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
+ if (likely(!mp->oom))
+ queue_mask |= mp->work_rx_refill;
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ if (!queue_mask) {
+ if (mv643xx_eth_collect_events(mp))
+ continue;
+ break;
+ }
- netif_rx_schedule(dev, &mp->napi);
+ queue = fls(queue_mask) - 1;
+ queue_mask = 1 << queue;
+
+ work_tbd = budget - work_done;
+ if (work_tbd > 16)
+ work_tbd = 16;
+
+ if (mp->work_tx_end & queue_mask) {
+ txq_kick(mp->txq + queue);
+ } else if (mp->work_tx & queue_mask) {
+ work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
+ txq_maybe_wake(mp->txq + queue);
+ } else if (mp->work_rx & queue_mask) {
+ work_done += rxq_process(mp->rxq + queue, work_tbd);
+ } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
+ work_done += rxq_refill(mp->rxq + queue, work_tbd);
+ } else {
+ BUG();
+ }
}
-#else
- if (int_cause & INT_RX)
- rxq_process(mp->rxq, INT_MAX);
-#endif
- if (int_cause_ext & INT_EXT_TX)
- mv643xx_eth_free_completed_tx_descs(dev);
- /*
- * If no real interrupt occured, exit.
- * This can happen when using gigE interrupt coalescing mechanism.
- */
- if ((int_cause == 0x0) && (int_cause_ext == 0x0))
- return IRQ_NONE;
+ if (work_done < budget) {
+ if (mp->oom)
+ mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
+ napi_complete(napi);
+ wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
+ }
- return IRQ_HANDLED;
+ return work_done;
+}
+
+static inline void oom_timer_wrapper(unsigned long data)
+{
+ struct mv643xx_eth_private *mp = (void *)data;
+
+ napi_schedule(&mp->napi);
}
static void phy_reset(struct mv643xx_eth_private *mp)
{
- unsigned int phy_reg_data;
+ int data;
+
+ data = phy_read(mp->phy, MII_BMCR);
+ if (data < 0)
+ return;
- /* Reset the PHY */
- read_smi_reg(mp, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- write_smi_reg(mp, 0, phy_reg_data);
+ data |= BMCR_RESET;
+ if (phy_write(mp->phy, MII_BMCR, data) < 0)
+ return;
- /* wait for PHY to come out of reset */
do {
- udelay(1);
- read_smi_reg(mp, 0, &phy_reg_data);
- } while (phy_reg_data & 0x8000);
+ data = phy_read(mp->phy, MII_BMCR);
+ } while (data >= 0 && data & BMCR_RESET);
}
-static void port_start(struct net_device *dev)
+static void port_start(struct mv643xx_eth_private *mp)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
u32 pscr;
- struct ethtool_cmd ethtool_cmd;
int i;
/*
+ * Perform PHY reset, if there is a PHY.
+ */
+ if (mp->phy != NULL) {
+ struct ethtool_cmd cmd;
+
+ mv643xx_eth_get_settings(mp->dev, &cmd);
+ phy_reset(mp);
+ mv643xx_eth_set_settings(mp->dev, &cmd);
+ }
+
+ /*
* Configure basic link parameters.
*/
- pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
- pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
- wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
- pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
- DISABLE_AUTO_NEG_SPEED_GMII |
- DISABLE_AUTO_NEG_FOR_DUPLEX |
- DO_NOT_FORCE_LINK_FAIL |
- SERIAL_PORT_CONTROL_RESERVED;
- wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
+ pscr = rdlp(mp, PORT_SERIAL_CONTROL);
+
pscr |= SERIAL_PORT_ENABLE;
- wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
+ wrlp(mp, PORT_SERIAL_CONTROL, pscr);
- wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
+ pscr |= DO_NOT_FORCE_LINK_FAIL;
+ if (mp->phy == NULL)
+ pscr |= FORCE_LINK_PASS;
+ wrlp(mp, PORT_SERIAL_CONTROL, pscr);
- mv643xx_eth_get_settings(dev, ðtool_cmd);
- phy_reset(mp);
- mv643xx_eth_set_settings(dev, ðtool_cmd);
+ /*
+ * Configure TX path and queues.
+ */
+ tx_set_rate(mp, 1000000000, 16777216);
+ for (i = 0; i < mp->txq_count; i++) {
+ struct tx_queue *txq = mp->txq + i;
- /* Add the assigned Ethernet address to the port's address table */
- uc_addr_set(mp, dev->dev_addr);
+ txq_reset_hw_ptr(txq);
+ txq_set_rate(txq, 1000000000, 16777216);
+ txq_set_fixed_prio_mode(txq);
+ }
/*
* Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
- * frames to RX queue #0.
+ * frames to RX queue #0, and include the pseudo-header when
+ * calculating receive checksums.
*/
- wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
+ wrlp(mp, PORT_CONFIG, 0x02000000);
/*
* Treat BPDUs as normal multicasts, and disable partition mode.
*/
- wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
+ wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
+
+ /*
+ * Add configured unicast addresses to address filter table.
+ */
+ mv643xx_eth_program_unicast_filter(mp->dev);
/*
- * Enable the receive queue.
+ * Enable the receive queues.
*/
- for (i = 0; i < 1; i++) {
- struct rx_queue *rxq = mp->rxq;
- int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
+ for (i = 0; i < mp->rxq_count; i++) {
+ struct rx_queue *rxq = mp->rxq + i;
u32 addr;
addr = (u32)rxq->rx_desc_dma;
addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
- wrl(mp, off, addr);
+ wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
rxq_enable(rxq);
}
-
-
- wrl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num),
- (u32)((struct tx_desc *)mp->tx_desc_dma + mp->tx_curr_desc));
-
- /* Disable port bandwidth limits by clearing MTU register */
- wrl(mp, TX_BW_MTU(mp->port_num), 0);
}
-#ifdef MV643XX_ETH_COAL
-static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
- unsigned int delay)
+static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
{
- unsigned int port_num = mp->port_num;
- unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
+ int skb_size;
- /* Set RX Coalescing mechanism */
- wrl(mp, SDMA_CONFIG(port_num),
- ((coal & 0x3fff) << 8) |
- (rdl(mp, SDMA_CONFIG(port_num))
- & 0xffc000ff));
-
- return coal;
-}
-#endif
-
-static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
- unsigned int delay)
-{
- unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
-
- /* Set TX Coalescing mechanism */
- wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
-
- return coal;
-}
-
-static void port_init(struct mv643xx_eth_private *mp)
-{
- port_reset(mp);
+ /*
+ * Reserve 2+14 bytes for an ethernet header (the hardware
+ * automatically prepends 2 bytes of dummy data to each
+ * received packet), 16 bytes for up to four VLAN tags, and
+ * 4 bytes for the trailing FCS -- 36 bytes total.
+ */
+ skb_size = mp->dev->mtu + 36;
- init_mac_tables(mp);
+ /*
+ * Make sure that the skb size is a multiple of 8 bytes, as
+ * the lower three bits of the receive descriptor's buffer
+ * size field are ignored by the hardware.
+ */
+ mp->skb_size = (skb_size + 7) & ~7;
}
static int mv643xx_eth_open(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
- unsigned int size;
int err;
+ int i;
- /* Clear any pending ethernet port interrupts */
- wrl(mp, INT_CAUSE(port_num), 0);
- wrl(mp, INT_CAUSE_EXT(port_num), 0);
- /* wait for previous write to complete */
- rdl(mp, INT_CAUSE_EXT(port_num));
+ wrlp(mp, INT_CAUSE, 0);
+ wrlp(mp, INT_CAUSE_EXT, 0);
+ rdlp(mp, INT_CAUSE_EXT);
- err = request_irq(dev->irq, mv643xx_eth_int_handler,
- IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
+ err = request_irq(dev->irq, mv643xx_eth_irq,
+ IRQF_SHARED, dev->name, dev);
if (err) {
- printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
+ dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
return -EAGAIN;
}
- port_init(mp);
+ mv643xx_eth_recalc_skb_size(mp);
- err = rxq_init(mp);
- if (err)
- goto out_free_irq;
- rxq_refill(mp->rxq);
-
- mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
- GFP_KERNEL);
- if (!mp->tx_skb) {
- printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
- err = -ENOMEM;
- goto out_free_rx_skb;
- }
-
- /* Allocate TX ring */
- mp->tx_desc_count = 0;
- size = mp->tx_ring_size * sizeof(struct tx_desc);
- mp->tx_desc_area_size = size;
-
- if (mp->tx_sram_size) {
- mp->tx_desc_area = ioremap(mp->tx_sram_addr,
- mp->tx_sram_size);
- mp->tx_desc_dma = mp->tx_sram_addr;
- } else
- mp->tx_desc_area = dma_alloc_coherent(NULL, size,
- &mp->tx_desc_dma,
- GFP_KERNEL);
-
- if (!mp->tx_desc_area) {
- printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
- dev->name, size);
- err = -ENOMEM;
- goto out_free_tx_skb;
- }
- BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
- memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
-
- ether_init_tx_desc_ring(mp);
-
-#ifdef MV643XX_ETH_NAPI
napi_enable(&mp->napi);
-#endif
- port_start(dev);
+ skb_queue_head_init(&mp->rx_recycle);
- /* Interrupt Coalescing */
+ for (i = 0; i < mp->rxq_count; i++) {
+ err = rxq_init(mp, i);
+ if (err) {
+ while (--i >= 0)
+ rxq_deinit(mp->rxq + i);
+ goto out;
+ }
-#ifdef MV643XX_ETH_COAL
- mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
-#endif
+ rxq_refill(mp->rxq + i, INT_MAX);
+ }
- mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
+ if (mp->oom) {
+ mp->rx_oom.expires = jiffies + (HZ / 10);
+ add_timer(&mp->rx_oom);
+ }
+
+ for (i = 0; i < mp->txq_count; i++) {
+ err = txq_init(mp, i);
+ if (err) {
+ while (--i >= 0)
+ txq_deinit(mp->txq + i);
+ goto out_free;
+ }
+ }
- /* Unmask phy and link status changes interrupts */
- wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
+ port_start(mp);
- /* Unmask RX buffer and TX end interrupt */
- wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
+ wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
+ wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
return 0;
-out_free_tx_skb:
- kfree(mp->tx_skb);
-out_free_rx_skb:
- rxq_deinit(mp->rxq);
-out_free_irq:
+
+out_free:
+ for (i = 0; i < mp->rxq_count; i++)
+ rxq_deinit(mp->rxq + i);
+out:
free_irq(dev->irq, dev);
return err;
static void port_reset(struct mv643xx_eth_private *mp)
{
- unsigned int port_num = mp->port_num;
- unsigned int reg_data;
+ unsigned int data;
+ int i;
- mv643xx_eth_port_disable_tx(mp);
- rxq_disable(mp->rxq);
+ for (i = 0; i < mp->rxq_count; i++)
+ rxq_disable(mp->rxq + i);
+ for (i = 0; i < mp->txq_count; i++)
+ txq_disable(mp->txq + i);
- /* Clear all MIB counters */
- clear_mib_counters(mp);
+ while (1) {
+ u32 ps = rdlp(mp, PORT_STATUS);
+
+ if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
+ break;
+ udelay(10);
+ }
/* Reset the Enable bit in the Configuration Register */
- reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
- reg_data &= ~(SERIAL_PORT_ENABLE |
- DO_NOT_FORCE_LINK_FAIL |
- FORCE_LINK_PASS);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
+ data = rdlp(mp, PORT_SERIAL_CONTROL);
+ data &= ~(SERIAL_PORT_ENABLE |
+ DO_NOT_FORCE_LINK_FAIL |
+ FORCE_LINK_PASS);
+ wrlp(mp, PORT_SERIAL_CONTROL, data);
}
static int mv643xx_eth_stop(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ int i;
- /* Mask all interrupts on ethernet port */
- wrl(mp, INT_MASK(port_num), 0x00000000);
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ wrlp(mp, INT_MASK_EXT, 0x00000000);
+ wrlp(mp, INT_MASK, 0x00000000);
+ rdlp(mp, INT_MASK);
-#ifdef MV643XX_ETH_NAPI
napi_disable(&mp->napi);
-#endif
+
+ del_timer_sync(&mp->rx_oom);
+
netif_carrier_off(dev);
- netif_stop_queue(dev);
+
+ free_irq(dev->irq, dev);
port_reset(mp);
+ mv643xx_eth_get_stats(dev);
+ mib_counters_update(mp);
+ del_timer_sync(&mp->mib_counters_timer);
- mv643xx_eth_free_tx_rings(dev);
- rxq_deinit(mp->rxq);
+ skb_queue_purge(&mp->rx_recycle);
- free_irq(dev->irq, dev);
+ for (i = 0; i < mp->rxq_count; i++)
+ rxq_deinit(mp->rxq + i);
+ for (i = 0; i < mp->txq_count; i++)
+ txq_deinit(mp->txq + i);
return 0;
}
-static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
+ if (mp->phy != NULL)
+ return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
+
+ return -EOPNOTSUPP;
}
static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
{
- if ((new_mtu > 9500) || (new_mtu < 64))
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ if (new_mtu < 64 || new_mtu > 9500)
return -EINVAL;
dev->mtu = new_mtu;
+ mv643xx_eth_recalc_skb_size(mp);
+ tx_set_rate(mp, 1000000000, 16777216);
+
if (!netif_running(dev))
return 0;
* Stop and then re-open the interface. This will allocate RX
* skbs of the new MTU.
* There is a possible danger that the open will not succeed,
- * due to memory being full, which might fail the open function.
+ * due to memory being full.
*/
mv643xx_eth_stop(dev);
if (mv643xx_eth_open(dev)) {
- printk(KERN_ERR "%s: Fatal error on opening device\n",
- dev->name);
+ dev_printk(KERN_ERR, &dev->dev,
+ "fatal error on re-opening device after "
+ "MTU change\n");
}
return 0;
}
-static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
+static void tx_timeout_task(struct work_struct *ugly)
{
- struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
- tx_timeout_task);
- struct net_device *dev = mp->dev;
-
- if (!netif_running(dev))
- return;
-
- netif_stop_queue(dev);
-
- port_reset(mp);
- port_start(dev);
+ struct mv643xx_eth_private *mp;
- if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
+ mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
+ if (netif_running(mp->dev)) {
+ netif_tx_stop_all_queues(mp->dev);
+ port_reset(mp);
+ port_start(mp);
+ netif_tx_wake_all_queues(mp->dev);
+ }
}
static void mv643xx_eth_tx_timeout(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- printk(KERN_INFO "%s: TX timeout ", dev->name);
+ dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
- /* Do the reset outside of interrupt context */
schedule_work(&mp->tx_timeout_task);
}
#ifdef CONFIG_NET_POLL_CONTROLLER
-static void mv643xx_eth_netpoll(struct net_device *netdev)
+static void mv643xx_eth_netpoll(struct net_device *dev)
{
- struct mv643xx_eth_private *mp = netdev_priv(netdev);
- int port_num = mp->port_num;
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
- wrl(mp, INT_MASK(port_num), 0x00000000);
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ wrlp(mp, INT_MASK, 0x00000000);
+ rdlp(mp, INT_MASK);
- mv643xx_eth_int_handler(netdev->irq, netdev);
+ mv643xx_eth_irq(dev->irq, dev);
- wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
+ wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
}
#endif
-static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- int val;
-
- read_smi_reg(mp, location, &val);
- return val;
-}
-
-static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- write_smi_reg(mp, location, val);
-}
-
/* platform glue ************************************************************/
static void
msp->win_protect = win_protect;
}
+static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
+{
+ /*
+ * Check whether we have a 14-bit coal limit field in bits
+ * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
+ * SDMA config register.
+ */
+ writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
+ if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
+ msp->extended_rx_coal_limit = 1;
+ else
+ msp->extended_rx_coal_limit = 0;
+
+ /*
+ * Check whether the MAC supports TX rate control, and if
+ * yes, whether its associated registers are in the old or
+ * the new place.
+ */
+ writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
+ if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
+ msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
+ } else {
+ writel(7, msp->base + 0x0400 + TX_BW_RATE);
+ if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
+ msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
+ else
+ msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
+ }
+}
+
static int mv643xx_eth_shared_probe(struct platform_device *pdev)
{
- static int mv643xx_eth_version_printed = 0;
+ static int mv643xx_eth_version_printed;
struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
struct mv643xx_eth_shared_private *msp;
struct resource *res;
int ret;
if (!mv643xx_eth_version_printed++)
- printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
+ printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
+ "driver version %s\n", mv643xx_eth_driver_version);
ret = -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (msp->base == NULL)
goto out_free;
- spin_lock_init(&msp->phy_lock);
- msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+ /*
+ * Set up and register SMI bus.
+ */
+ if (pd == NULL || pd->shared_smi == NULL) {
+ msp->smi_bus = mdiobus_alloc();
+ if (msp->smi_bus == NULL)
+ goto out_unmap;
+
+ msp->smi_bus->priv = msp;
+ msp->smi_bus->name = "mv643xx_eth smi";
+ msp->smi_bus->read = smi_bus_read;
+ msp->smi_bus->write = smi_bus_write,
+ snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
+ msp->smi_bus->parent = &pdev->dev;
+ msp->smi_bus->phy_mask = 0xffffffff;
+ if (mdiobus_register(msp->smi_bus) < 0)
+ goto out_free_mii_bus;
+ msp->smi = msp;
+ } else {
+ msp->smi = platform_get_drvdata(pd->shared_smi);
+ }
- platform_set_drvdata(pdev, msp);
+ msp->err_interrupt = NO_IRQ;
+ init_waitqueue_head(&msp->smi_busy_wait);
+
+ /*
+ * Check whether the error interrupt is hooked up.
+ */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res != NULL) {
+ int err;
+
+ err = request_irq(res->start, mv643xx_eth_err_irq,
+ IRQF_SHARED, "mv643xx_eth", msp);
+ if (!err) {
+ writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
+ msp->err_interrupt = res->start;
+ }
+ }
/*
* (Re-)program MBUS remapping windows if we are asked to.
if (pd != NULL && pd->dram != NULL)
mv643xx_eth_conf_mbus_windows(msp, pd->dram);
+ /*
+ * Detect hardware parameters.
+ */
+ msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+ infer_hw_params(msp);
+
+ platform_set_drvdata(pdev, msp);
+
return 0;
+out_free_mii_bus:
+ mdiobus_free(msp->smi_bus);
+out_unmap:
+ iounmap(msp->base);
out_free:
kfree(msp);
out:
static int mv643xx_eth_shared_remove(struct platform_device *pdev)
{
struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
+ struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
+ if (pd == NULL || pd->shared_smi == NULL) {
+ mdiobus_unregister(msp->smi_bus);
+ mdiobus_free(msp->smi_bus);
+ }
+ if (msp->err_interrupt != NO_IRQ)
+ free_irq(msp->err_interrupt, msp);
iounmap(msp->base);
kfree(msp);
}
static struct platform_driver mv643xx_eth_shared_driver = {
- .probe = mv643xx_eth_shared_probe,
- .remove = mv643xx_eth_shared_remove,
+ .probe = mv643xx_eth_shared_probe,
+ .remove = mv643xx_eth_shared_remove,
.driver = {
- .name = MV643XX_ETH_SHARED_NAME,
+ .name = MV643XX_ETH_SHARED_NAME,
.owner = THIS_MODULE,
},
};
static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
{
- u32 reg_data;
int addr_shift = 5 * mp->port_num;
+ u32 data;
- reg_data = rdl(mp, PHY_ADDR);
- reg_data &= ~(0x1f << addr_shift);
- reg_data |= (phy_addr & 0x1f) << addr_shift;
- wrl(mp, PHY_ADDR, reg_data);
+ data = rdl(mp, PHY_ADDR);
+ data &= ~(0x1f << addr_shift);
+ data |= (phy_addr & 0x1f) << addr_shift;
+ wrl(mp, PHY_ADDR, data);
}
static int phy_addr_get(struct mv643xx_eth_private *mp)
{
- unsigned int reg_data;
+ unsigned int data;
- reg_data = rdl(mp, PHY_ADDR);
+ data = rdl(mp, PHY_ADDR);
- return ((reg_data >> (5 * mp->port_num)) & 0x1f);
+ return (data >> (5 * mp->port_num)) & 0x1f;
}
-static int phy_detect(struct mv643xx_eth_private *mp)
+static void set_params(struct mv643xx_eth_private *mp,
+ struct mv643xx_eth_platform_data *pd)
{
- unsigned int phy_reg_data0;
- int auto_neg;
+ struct net_device *dev = mp->dev;
+
+ if (is_valid_ether_addr(pd->mac_addr))
+ memcpy(dev->dev_addr, pd->mac_addr, 6);
+ else
+ uc_addr_get(mp, dev->dev_addr);
- read_smi_reg(mp, 0, &phy_reg_data0);
- auto_neg = phy_reg_data0 & 0x1000;
- phy_reg_data0 ^= 0x1000; /* invert auto_neg */
- write_smi_reg(mp, 0, phy_reg_data0);
+ mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
+ if (pd->rx_queue_size)
+ mp->rx_ring_size = pd->rx_queue_size;
+ mp->rx_desc_sram_addr = pd->rx_sram_addr;
+ mp->rx_desc_sram_size = pd->rx_sram_size;
- read_smi_reg(mp, 0, &phy_reg_data0);
- if ((phy_reg_data0 & 0x1000) == auto_neg)
- return -ENODEV; /* change didn't take */
+ mp->rxq_count = pd->rx_queue_count ? : 1;
- phy_reg_data0 ^= 0x1000;
- write_smi_reg(mp, 0, phy_reg_data0);
- return 0;
+ mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
+ if (pd->tx_queue_size)
+ mp->tx_ring_size = pd->tx_queue_size;
+ mp->tx_desc_sram_addr = pd->tx_sram_addr;
+ mp->tx_desc_sram_size = pd->tx_sram_size;
+
+ mp->txq_count = pd->tx_queue_count ? : 1;
}
-static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
- int speed, int duplex,
- struct ethtool_cmd *cmd)
+static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
+ int phy_addr)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
+ struct mii_bus *bus = mp->shared->smi->smi_bus;
+ struct phy_device *phydev;
+ int start;
+ int num;
+ int i;
- memset(cmd, 0, sizeof(*cmd));
+ if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
+ start = phy_addr_get(mp) & 0x1f;
+ num = 32;
+ } else {
+ start = phy_addr & 0x1f;
+ num = 1;
+ }
- cmd->port = PORT_MII;
- cmd->transceiver = XCVR_INTERNAL;
- cmd->phy_address = phy_address;
+ phydev = NULL;
+ for (i = 0; i < num; i++) {
+ int addr = (start + i) & 0x1f;
+
+ if (bus->phy_map[addr] == NULL)
+ mdiobus_scan(bus, addr);
+
+ if (phydev == NULL) {
+ phydev = bus->phy_map[addr];
+ if (phydev != NULL)
+ phy_addr_set(mp, addr);
+ }
+ }
+
+ return phydev;
+}
+
+static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
+{
+ struct phy_device *phy = mp->phy;
+
+ phy_reset(mp);
+
+ phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
if (speed == 0) {
- cmd->autoneg = AUTONEG_ENABLE;
- /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
- cmd->speed = SPEED_100;
- cmd->advertising = ADVERTISED_10baseT_Half |
- ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half |
- ADVERTISED_100baseT_Full;
- if (mp->mii.supports_gmii)
- cmd->advertising |= ADVERTISED_1000baseT_Full;
+ phy->autoneg = AUTONEG_ENABLE;
+ phy->speed = 0;
+ phy->duplex = 0;
+ phy->advertising = phy->supported | ADVERTISED_Autoneg;
} else {
- cmd->autoneg = AUTONEG_DISABLE;
- cmd->speed = speed;
- cmd->duplex = duplex;
+ phy->autoneg = AUTONEG_DISABLE;
+ phy->advertising = 0;
+ phy->speed = speed;
+ phy->duplex = duplex;
+ }
+ phy_start_aneg(phy);
+}
+
+static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
+{
+ u32 pscr;
+
+ pscr = rdlp(mp, PORT_SERIAL_CONTROL);
+ if (pscr & SERIAL_PORT_ENABLE) {
+ pscr &= ~SERIAL_PORT_ENABLE;
+ wrlp(mp, PORT_SERIAL_CONTROL, pscr);
+ }
+
+ pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
+ if (mp->phy == NULL) {
+ pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
+ if (speed == SPEED_1000)
+ pscr |= SET_GMII_SPEED_TO_1000;
+ else if (speed == SPEED_100)
+ pscr |= SET_MII_SPEED_TO_100;
+
+ pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
+
+ pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
+ if (duplex == DUPLEX_FULL)
+ pscr |= SET_FULL_DUPLEX_MODE;
}
+
+ wrlp(mp, PORT_SERIAL_CONTROL, pscr);
}
+static const struct net_device_ops mv643xx_eth_netdev_ops = {
+ .ndo_open = mv643xx_eth_open,
+ .ndo_stop = mv643xx_eth_stop,
+ .ndo_start_xmit = mv643xx_eth_xmit,
+ .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
+ .ndo_set_mac_address = mv643xx_eth_set_mac_address,
+ .ndo_do_ioctl = mv643xx_eth_ioctl,
+ .ndo_change_mtu = mv643xx_eth_change_mtu,
+ .ndo_tx_timeout = mv643xx_eth_tx_timeout,
+ .ndo_get_stats = mv643xx_eth_get_stats,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = mv643xx_eth_netpoll,
+#endif
+};
+
static int mv643xx_eth_probe(struct platform_device *pdev)
{
struct mv643xx_eth_platform_data *pd;
- int port_num;
struct mv643xx_eth_private *mp;
struct net_device *dev;
- u8 *p;
struct resource *res;
int err;
- struct ethtool_cmd cmd;
- int duplex = DUPLEX_HALF;
- int speed = 0; /* default to auto-negotiation */
- DECLARE_MAC_BUF(mac);
pd = pdev->dev.platform_data;
if (pd == NULL) {
- printk(KERN_ERR "No mv643xx_eth_platform_data\n");
+ dev_printk(KERN_ERR, &pdev->dev,
+ "no mv643xx_eth_platform_data\n");
return -ENODEV;
}
if (pd->shared == NULL) {
- printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
+ dev_printk(KERN_ERR, &pdev->dev,
+ "no mv643xx_eth_platform_data->shared\n");
return -ENODEV;
}
- dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
+ dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
if (!dev)
return -ENOMEM;
- platform_set_drvdata(pdev, dev);
-
mp = netdev_priv(dev);
- mp->dev = dev;
-#ifdef MV643XX_ETH_NAPI
- netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
-#endif
+ platform_set_drvdata(pdev, mp);
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- BUG_ON(!res);
- dev->irq = res->start;
+ mp->shared = platform_get_drvdata(pd->shared);
+ mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
+ mp->port_num = pd->port_number;
- dev->open = mv643xx_eth_open;
- dev->stop = mv643xx_eth_stop;
- dev->hard_start_xmit = mv643xx_eth_start_xmit;
- dev->set_mac_address = mv643xx_eth_set_mac_address;
- dev->set_multicast_list = mv643xx_eth_set_rx_mode;
+ mp->dev = dev;
- /* No need to Tx Timeout */
- dev->tx_timeout = mv643xx_eth_tx_timeout;
+ set_params(mp, pd);
+ dev->real_num_tx_queues = mp->txq_count;
-#ifdef CONFIG_NET_POLL_CONTROLLER
- dev->poll_controller = mv643xx_eth_netpoll;
-#endif
+ if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
+ mp->phy = phy_scan(mp, pd->phy_addr);
+
+ if (mp->phy != NULL)
+ phy_init(mp, pd->speed, pd->duplex);
- dev->watchdog_timeo = 2 * HZ;
- dev->base_addr = 0;
- dev->change_mtu = mv643xx_eth_change_mtu;
- dev->do_ioctl = mv643xx_eth_do_ioctl;
SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
-#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
-#ifdef MAX_SKB_FRAGS
- /*
- * Zero copy can only work if we use Discovery II memory. Else, we will
- * have to map the buffers to ISA memory which is only 16 MB
- */
- dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
-#endif
-#endif
+ init_pscr(mp, pd->speed, pd->duplex);
- /* Configure the timeout task */
- INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
- spin_lock_init(&mp->lock);
+ mib_counters_clear(mp);
- mp->shared = platform_get_drvdata(pd->shared);
- port_num = mp->port_num = pd->port_number;
+ init_timer(&mp->mib_counters_timer);
+ mp->mib_counters_timer.data = (unsigned long)mp;
+ mp->mib_counters_timer.function = mib_counters_timer_wrapper;
+ mp->mib_counters_timer.expires = jiffies + 30 * HZ;
+ add_timer(&mp->mib_counters_timer);
- if (mp->shared->win_protect)
- wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
+ spin_lock_init(&mp->mib_counters_lock);
- mp->shared_smi = mp->shared;
- if (pd->shared_smi != NULL)
- mp->shared_smi = platform_get_drvdata(pd->shared_smi);
+ INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
- /* set default config values */
- uc_addr_get(mp, dev->dev_addr);
- mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
+ netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
- if (is_valid_ether_addr(pd->mac_addr))
- memcpy(dev->dev_addr, pd->mac_addr, 6);
+ init_timer(&mp->rx_oom);
+ mp->rx_oom.data = (unsigned long)mp;
+ mp->rx_oom.function = oom_timer_wrapper;
- if (pd->phy_addr || pd->force_phy_addr)
- phy_addr_set(mp, pd->phy_addr);
- mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
- if (pd->rx_queue_size)
- mp->default_rx_ring_size = pd->rx_queue_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ BUG_ON(!res);
+ dev->irq = res->start;
- if (pd->tx_queue_size)
- mp->tx_ring_size = pd->tx_queue_size;
+ dev->netdev_ops = &mv643xx_eth_netdev_ops;
- if (pd->tx_sram_size) {
- mp->tx_sram_size = pd->tx_sram_size;
- mp->tx_sram_addr = pd->tx_sram_addr;
- }
+ dev->watchdog_timeo = 2 * HZ;
+ dev->base_addr = 0;
- if (pd->rx_sram_size) {
- mp->rx_desc_sram_addr = pd->rx_sram_addr;
- mp->rx_desc_sram_size = pd->rx_sram_size;
- }
+ dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
+ dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
- duplex = pd->duplex;
- speed = pd->speed;
+ SET_NETDEV_DEV(dev, &pdev->dev);
- /* Hook up MII support for ethtool */
- mp->mii.dev = dev;
- mp->mii.mdio_read = mv643xx_eth_mdio_read;
- mp->mii.mdio_write = mv643xx_eth_mdio_write;
- mp->mii.phy_id = phy_addr_get(mp);
- mp->mii.phy_id_mask = 0x3f;
- mp->mii.reg_num_mask = 0x1f;
+ if (mp->shared->win_protect)
+ wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
- err = phy_detect(mp);
- if (err) {
- pr_debug("%s: No PHY detected at addr %d\n",
- dev->name, phy_addr_get(mp));
- goto out;
- }
+ netif_carrier_off(dev);
- phy_reset(mp);
- mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
- mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
- mv643xx_eth_update_pscr(dev, &cmd);
- mv643xx_eth_set_settings(dev, &cmd);
+ wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
+
+ set_rx_coal(mp, 250);
+ set_tx_coal(mp, 0);
- SET_NETDEV_DEV(dev, &pdev->dev);
err = register_netdev(dev);
if (err)
goto out;
- p = dev->dev_addr;
- printk(KERN_NOTICE
- "%s: port %d with MAC address %s\n",
- dev->name, port_num, print_mac(mac, p));
-
- if (dev->features & NETIF_F_SG)
- printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
-
- if (dev->features & NETIF_F_IP_CSUM)
- printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
- dev->name);
-
-#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
- printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
-#endif
-
-#ifdef MV643XX_ETH_COAL
- printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
- dev->name);
-#endif
-
-#ifdef MV643XX_ETH_NAPI
- printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
-#endif
+ dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
+ mp->port_num, dev->dev_addr);
- if (mp->tx_sram_size > 0)
- printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
+ if (mp->tx_desc_sram_size > 0)
+ dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
return 0;
static int mv643xx_eth_remove(struct platform_device *pdev)
{
- struct net_device *dev = platform_get_drvdata(pdev);
+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
- unregister_netdev(dev);
+ unregister_netdev(mp->dev);
+ if (mp->phy != NULL)
+ phy_detach(mp->phy);
flush_scheduled_work();
+ free_netdev(mp->dev);
- free_netdev(dev);
platform_set_drvdata(pdev, NULL);
+
return 0;
}
static void mv643xx_eth_shutdown(struct platform_device *pdev)
{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
/* Mask all interrupts on ethernet port */
- wrl(mp, INT_MASK(port_num), 0);
- rdl(mp, INT_MASK(port_num));
+ wrlp(mp, INT_MASK, 0);
+ rdlp(mp, INT_MASK);
- port_reset(mp);
+ if (netif_running(mp->dev))
+ port_reset(mp);
}
static struct platform_driver mv643xx_eth_driver = {
- .probe = mv643xx_eth_probe,
- .remove = mv643xx_eth_remove,
- .shutdown = mv643xx_eth_shutdown,
+ .probe = mv643xx_eth_probe,
+ .remove = mv643xx_eth_remove,
+ .shutdown = mv643xx_eth_shutdown,
.driver = {
- .name = MV643XX_ETH_NAME,
+ .name = MV643XX_ETH_NAME,
.owner = THIS_MODULE,
},
};
if (rc)
platform_driver_unregister(&mv643xx_eth_shared_driver);
}
+
return rc;
}
+module_init(mv643xx_eth_init_module);
static void __exit mv643xx_eth_cleanup_module(void)
{
platform_driver_unregister(&mv643xx_eth_driver);
platform_driver_unregister(&mv643xx_eth_shared_driver);
}
-
-module_init(mv643xx_eth_init_module);
module_exit(mv643xx_eth_cleanup_module);
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
- " and Dale Farnsworth");
+MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
+ "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
-MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
+MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
+MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff