* Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
*
* Based on the 64360 driver from:
- * Copyright (C) 2002 rabeeh@galileo.co.il
+ * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
+ * Rabeeh Khoury <rabeeh@marvell.com>
*
* Copyright (C) 2003 PMC-Sierra, Inc.,
* written by Manish Lachwani
* Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
* <sjhill@realitydiluted.com>
*
+ * Copyright (C) 2007-2008 Marvell Semiconductor
+ * Lennert Buytenhek <buytenh@marvell.com>
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
/* Static function declarations */
static void eth_port_init(struct mv643xx_private *mp);
-static void eth_port_reset(unsigned int eth_port_num);
+static void eth_port_reset(struct mv643xx_private *mp);
static void eth_port_start(struct net_device *dev);
-static void ethernet_phy_reset(unsigned int eth_port_num);
+static void ethernet_phy_reset(struct mv643xx_private *mp);
-static void eth_port_write_smi_reg(unsigned int eth_port_num,
+static void eth_port_write_smi_reg(struct mv643xx_private *mp,
unsigned int phy_reg, unsigned int value);
-static void eth_port_read_smi_reg(unsigned int eth_port_num,
+static void eth_port_read_smi_reg(struct mv643xx_private *mp,
unsigned int phy_reg, unsigned int *value);
-static void eth_clear_mib_counters(unsigned int eth_port_num);
+static void eth_clear_mib_counters(struct mv643xx_private *mp);
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
-static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
-static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
+static void eth_port_uc_addr_get(struct mv643xx_private *mp,
+ unsigned char *p_addr);
+static void eth_port_uc_addr_set(struct mv643xx_private *mp,
+ unsigned char *p_addr);
static void eth_port_set_multicast_list(struct net_device *);
-static void mv643xx_eth_port_enable_tx(unsigned int port_num,
+static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
unsigned int queues);
-static void mv643xx_eth_port_enable_rx(unsigned int port_num,
+static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
unsigned int queues);
-static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
-static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
+static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
+static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
static int mv643xx_eth_open(struct net_device *);
static int mv643xx_eth_stop(struct net_device *);
-static void eth_port_init_mac_tables(unsigned int eth_port_num);
+static void eth_port_init_mac_tables(struct mv643xx_private *mp);
#ifdef MV643XX_NAPI
static int mv643xx_poll(struct napi_struct *napi, int budget);
#endif
-static int ethernet_phy_get(unsigned int eth_port_num);
-static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
-static int ethernet_phy_detect(unsigned int eth_port_num);
+static int ethernet_phy_get(struct mv643xx_private *mp);
+static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
+static int ethernet_phy_detect(struct mv643xx_private *mp);
static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
/* used to protect SMI_REG, which is shared across ports */
static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
-static inline u32 mv_read(int offset)
+static inline u32 rdl(struct mv643xx_private *mp, int offset)
{
return readl(mv643xx_eth_base + offset);
}
-static inline void mv_write(int offset, u32 data)
+static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
{
writel(data, mv643xx_eth_base + offset);
}
static void mv643xx_eth_update_mac_address(struct net_device *dev)
{
struct mv643xx_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
- eth_port_init_mac_tables(port_num);
- eth_port_uc_addr_set(port_num, dev->dev_addr);
+ eth_port_init_mac_tables(mp);
+ eth_port_uc_addr_set(mp, dev->dev_addr);
}
/*
struct mv643xx_private *mp = netdev_priv(dev);
u32 config_reg;
- config_reg = mv_read(PORT_CONFIG_REG(mp->port_num));
+ config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num));
if (dev->flags & IFF_PROMISC)
config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
else
config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
- mv_write(PORT_CONFIG_REG(mp->port_num), config_reg);
+ wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
eth_port_set_multicast_list(dev);
}
netif_stop_queue(dev);
- eth_port_reset(mp->port_num);
+ eth_port_reset(mp);
eth_port_start(dev);
if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
u32 o_pscr, n_pscr;
unsigned int queues;
- o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
+ o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
n_pscr = o_pscr;
/* clear speed, duplex and rx buffer size fields */
if (n_pscr != o_pscr) {
if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
else {
- queues = mv643xx_eth_port_disable_tx(port_num);
+ queues = mv643xx_eth_port_disable_tx(mp);
o_pscr &= ~SERIAL_PORT_ENABLE;
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
if (queues)
- mv643xx_eth_port_enable_tx(port_num, queues);
+ mv643xx_eth_port_enable_tx(mp, queues);
}
}
}
unsigned int port_num = mp->port_num;
/* Read interrupt cause registers */
- eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) &
+ eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
ETH_INT_UNMASK_ALL;
if (eth_int_cause & ETH_INT_CAUSE_EXT) {
- eth_int_cause_ext = mv_read(
+ eth_int_cause_ext = rdl(mp,
INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
ETH_INT_UNMASK_ALL_EXT;
- mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num),
+ wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
~eth_int_cause_ext);
}
if (mii_link_ok(&mp->mii)) {
mii_ethtool_gset(&mp->mii, &cmd);
mv643xx_eth_update_pscr(dev, &cmd);
- mv643xx_eth_port_enable_tx(port_num,
- ETH_TX_QUEUES_ENABLED);
+ mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
if (!netif_carrier_ok(dev)) {
netif_carrier_on(dev);
if (mp->tx_ring_size - mp->tx_desc_count >=
#ifdef MV643XX_NAPI
if (eth_int_cause & ETH_INT_CAUSE_RX) {
/* schedule the NAPI poll routine to maintain port */
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
/* wait for previous write to complete */
- mv_read(INTERRUPT_MASK_REG(port_num));
+ rdl(mp, INTERRUPT_MASK_REG(port_num));
netif_rx_schedule(dev, &mp->napi);
}
* , and the required delay of the interrupt in usec.
*
* INPUT:
- * unsigned int eth_port_num Ethernet port number
+ * struct mv643xx_private *mp Ethernet port
* unsigned int t_clk t_clk of the MV-643xx chip in HZ units
* unsigned int delay Delay in usec
*
* The interrupt coalescing value set in the gigE port.
*
*/
-static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
+static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
unsigned int t_clk, unsigned int delay)
{
+ unsigned int port_num = mp->port_num;
unsigned int coal = ((t_clk / 1000000) * delay) / 64;
/* Set RX Coalescing mechanism */
- mv_write(SDMA_CONFIG_REG(eth_port_num),
+ wrl(mp, SDMA_CONFIG_REG(port_num),
((coal & 0x3fff) << 8) |
- (mv_read(SDMA_CONFIG_REG(eth_port_num))
+ (rdl(mp, SDMA_CONFIG_REG(port_num))
& 0xffc000ff));
return coal;
* MV-643xx chip and the required delay in the interrupt in uSec
*
* INPUT:
- * unsigned int eth_port_num Ethernet port number
+ * struct mv643xx_private *mp Ethernet port
* unsigned int t_clk t_clk of the MV-643xx chip in HZ units
* unsigned int delay Delay in uSeconds
*
* The interrupt coalescing value set in the gigE port.
*
*/
-static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
+static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
unsigned int t_clk, unsigned int delay)
{
- unsigned int coal;
- coal = ((t_clk / 1000000) * delay) / 64;
+ unsigned int coal = ((t_clk / 1000000) * delay) / 64;
+
/* Set TX Coalescing mechanism */
- mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4);
+ wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4);
+
return coal;
}
int err;
/* Clear any pending ethernet port interrupts */
- mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
- mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+ wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
+ wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
/* wait for previous write to complete */
- mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num));
+ rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
err = request_irq(dev->irq, mv643xx_eth_int_handler,
IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
if (err) {
- printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
- port_num);
+ printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
return -EAGAIN;
}
#ifdef MV643XX_COAL
mp->rx_int_coal =
- eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
+ eth_port_set_rx_coal(mp, 133000000, MV643XX_RX_COAL);
#endif
mp->tx_int_coal =
- eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
+ eth_port_set_tx_coal(mp, 133000000, MV643XX_TX_COAL);
/* Unmask phy and link status changes interrupts */
- mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
+ wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
/* Unmask RX buffer and TX end interrupt */
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
return 0;
struct mv643xx_private *mp = netdev_priv(dev);
/* Stop Tx Queues */
- mv643xx_eth_port_disable_tx(mp->port_num);
+ mv643xx_eth_port_disable_tx(mp);
/* Free outstanding skb's on TX ring */
mv643xx_eth_free_all_tx_descs(dev);
static void mv643xx_eth_free_rx_rings(struct net_device *dev)
{
struct mv643xx_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
int curr;
/* Stop RX Queues */
- mv643xx_eth_port_disable_rx(port_num);
+ mv643xx_eth_port_disable_rx(mp);
/* Free preallocated skb's on RX rings */
for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
unsigned int port_num = mp->port_num;
/* Mask all interrupts on ethernet port */
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
/* wait for previous write to complete */
- mv_read(INTERRUPT_MASK_REG(port_num));
+ rdl(mp, INTERRUPT_MASK_REG(port_num));
#ifdef MV643XX_NAPI
napi_disable(&mp->napi);
netif_carrier_off(dev);
netif_stop_queue(dev);
- eth_port_reset(mp->port_num);
+ eth_port_reset(mp);
mv643xx_eth_free_tx_rings(dev);
mv643xx_eth_free_rx_rings(dev);
#endif
work_done = 0;
- if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
+ if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
!= (u32) mp->rx_used_desc_q)
work_done = mv643xx_eth_receive_queue(dev, budget);
if (work_done < budget) {
netif_rx_complete(dev, napi);
- mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
- mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
+ wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
+ wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
}
return work_done;
/* ensure all descriptors are written before poking hardware */
wmb();
- mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
+ mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
mp->tx_desc_count += nr_frags + 1;
}
struct mv643xx_private *mp = netdev_priv(netdev);
int port_num = mp->port_num;
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
/* wait for previous write to complete */
- mv_read(INTERRUPT_MASK_REG(port_num));
+ rdl(mp, INTERRUPT_MASK_REG(port_num));
mv643xx_eth_int_handler(netdev->irq, netdev);
- mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
+ wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
}
#endif
port_num = mp->port_num = pd->port_number;
/* set default config values */
- eth_port_uc_addr_get(port_num, dev->dev_addr);
+ eth_port_uc_addr_get(mp, dev->dev_addr);
mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
memcpy(dev->dev_addr, pd->mac_addr, 6);
if (pd->phy_addr || pd->force_phy_addr)
- ethernet_phy_set(port_num, pd->phy_addr);
+ ethernet_phy_set(mp, pd->phy_addr);
if (pd->rx_queue_size)
mp->rx_ring_size = pd->rx_queue_size;
mp->mii.dev = dev;
mp->mii.mdio_read = mv643xx_mdio_read;
mp->mii.mdio_write = mv643xx_mdio_write;
- mp->mii.phy_id = ethernet_phy_get(port_num);
+ mp->mii.phy_id = ethernet_phy_get(mp);
mp->mii.phy_id_mask = 0x3f;
mp->mii.reg_num_mask = 0x1f;
- err = ethernet_phy_detect(port_num);
+ err = ethernet_phy_detect(mp);
if (err) {
- pr_debug("MV643xx ethernet port %d: "
- "No PHY detected at addr %d\n",
- port_num, ethernet_phy_get(port_num));
+ pr_debug("%s: No PHY detected at addr %d\n",
+ dev->name, ethernet_phy_get(mp));
goto out;
}
- ethernet_phy_reset(port_num);
+ ethernet_phy_reset(mp);
mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
mv643xx_eth_update_pscr(dev, &cmd);
static int mv643xx_eth_shared_probe(struct platform_device *pdev)
{
+ static int mv643xx_version_printed = 0;
struct resource *res;
- printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
+ if (!mv643xx_version_printed++)
+ printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
unsigned int port_num = mp->port_num;
/* Mask all interrupts on ethernet port */
- mv_write(INTERRUPT_MASK_REG(port_num), 0);
- mv_read (INTERRUPT_MASK_REG(port_num));
+ wrl(mp, INTERRUPT_MASK_REG(port_num), 0);
+ rdl(mp, INTERRUPT_MASK_REG(port_num));
- eth_port_reset(port_num);
+ eth_port_reset(mp);
}
static struct platform_driver mv643xx_eth_driver = {
.shutdown = mv643xx_eth_shutdown,
.driver = {
.name = MV643XX_ETH_NAME,
+ .owner = THIS_MODULE,
},
};
.remove = mv643xx_eth_shared_remove,
.driver = {
.name = MV643XX_ETH_SHARED_NAME,
+ .owner = THIS_MODULE,
},
};
MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
" and Dale Farnsworth");
MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
-MODULE_ALIAS("platform:mv643xx_eth");
+MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
+MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
/*
* The second part is the low level driver of the gigE ethernet ports.
* return_info Tx/Rx user resource return information.
*/
-/* PHY routines */
-static int ethernet_phy_get(unsigned int eth_port_num);
-static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
-
/* Ethernet Port routines */
-static void eth_port_set_filter_table_entry(int table, unsigned char entry);
+static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
+ int table, unsigned char entry);
/*
* eth_port_init - Initialize the Ethernet port driver
{
mp->rx_resource_err = 0;
- eth_port_reset(mp->port_num);
+ eth_port_reset(mp);
- eth_port_init_mac_tables(mp->port_num);
+ eth_port_init_mac_tables(mp);
}
/*
/* Assignment of Tx CTRP of given queue */
tx_curr_desc = mp->tx_curr_desc_q;
- mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
+ wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
(u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
/* Assignment of Rx CRDP of given queue */
rx_curr_desc = mp->rx_curr_desc_q;
- mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
+ wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
(u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
/* Add the assigned Ethernet address to the port's address table */
- eth_port_uc_addr_set(port_num, dev->dev_addr);
+ eth_port_uc_addr_set(mp, dev->dev_addr);
/* Assign port configuration and command. */
- mv_write(PORT_CONFIG_REG(port_num),
+ wrl(mp, PORT_CONFIG_REG(port_num),
PORT_CONFIG_DEFAULT_VALUE);
- mv_write(PORT_CONFIG_EXTEND_REG(port_num),
+ wrl(mp, PORT_CONFIG_EXTEND_REG(port_num),
PORT_CONFIG_EXTEND_DEFAULT_VALUE);
- pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
+ pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
DISABLE_AUTO_NEG_SPEED_GMII |
DO_NOT_FORCE_LINK_FAIL |
SERIAL_PORT_CONTROL_RESERVED;
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
pscr |= SERIAL_PORT_ENABLE;
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
/* Assign port SDMA configuration */
- mv_write(SDMA_CONFIG_REG(port_num),
+ wrl(mp, SDMA_CONFIG_REG(port_num),
PORT_SDMA_CONFIG_DEFAULT_VALUE);
/* Enable port Rx. */
- mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
+ mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
/* Disable port bandwidth limits by clearing MTU register */
- mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0);
+ wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0);
/* save phy settings across reset */
mv643xx_get_settings(dev, ðtool_cmd);
- ethernet_phy_reset(mp->port_num);
+ ethernet_phy_reset(mp);
mv643xx_set_settings(dev, ðtool_cmd);
}
/*
* eth_port_uc_addr_set - Write a MAC address into the port's hw registers
*/
-static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
+static void eth_port_uc_addr_set(struct mv643xx_private *mp,
+ unsigned char *p_addr)
{
+ unsigned int port_num = mp->port_num;
unsigned int mac_h;
unsigned int mac_l;
int table;
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
- mv_write(MAC_ADDR_LOW(port_num), mac_l);
- mv_write(MAC_ADDR_HIGH(port_num), mac_h);
+ wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
+ wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
/* Accept frames with this address */
table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
- eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
+ eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
}
/*
* eth_port_uc_addr_get - Read the MAC address from the port's hw registers
*/
-static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
+static void eth_port_uc_addr_get(struct mv643xx_private *mp,
+ unsigned char *p_addr)
{
+ unsigned int port_num = mp->port_num;
unsigned int mac_h;
unsigned int mac_l;
- mac_h = mv_read(MAC_ADDR_HIGH(port_num));
- mac_l = mv_read(MAC_ADDR_LOW(port_num));
+ mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
+ mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
p_addr[0] = (mac_h >> 24) & 0xff;
p_addr[1] = (mac_h >> 16) & 0xff;
* 3-1 Queue (ETH_Q0=0)
* 7-4 Reserved = 0;
*/
-static void eth_port_set_filter_table_entry(int table, unsigned char entry)
+static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
+ int table, unsigned char entry)
{
unsigned int table_reg;
unsigned int tbl_offset;
reg_offset = entry % 4; /* Entry offset within the register */
/* Set "accepts frame bit" at specified table entry */
- table_reg = mv_read(table + tbl_offset);
+ table_reg = rdl(mp, table + tbl_offset);
table_reg |= 0x01 << (8 * reg_offset);
- mv_write(table + tbl_offset, table_reg);
+ wrl(mp, table + tbl_offset, table_reg);
}
/*
* In either case, eth_port_set_filter_table_entry() is then called
* to set to set the actual table entry.
*/
-static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
+static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
{
+ unsigned int port_num = mp->port_num;
unsigned int mac_h;
unsigned int mac_l;
unsigned char crc_result = 0;
if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
(p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
- table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
- (eth_port_num);
- eth_port_set_filter_table_entry(table, p_addr[5]);
+ table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num);
+ eth_port_set_filter_table_entry(mp, table, p_addr[5]);
return;
}
for (i = 0; i < 8; i++)
crc_result = crc_result | (crc[i] << i);
- table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
- eth_port_set_filter_table_entry(table, crc_result);
+ table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num);
+ eth_port_set_filter_table_entry(mp, table, crc_result);
}
/*
* 3-1 Queue ETH_Q0=0
* 7-4 Reserved = 0;
*/
- mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
+ wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
/* Set all entries in DA filter other multicast
* table (Ex_dFOMT)
* 3-1 Queue ETH_Q0=0
* 7-4 Reserved = 0;
*/
- mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
+ wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
}
return;
}
*/
for (table_index = 0; table_index <= 0xFC; table_index += 4) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
- mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
+ wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
- mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
+ wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0);
}
(i < 256) && (mc_list != NULL) && (i < dev->mc_count);
i++, mc_list = mc_list->next)
if (mc_list->dmi_addrlen == 6)
- eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
+ eth_port_mc_addr(mp, mc_list->dmi_addr);
}
/*
* Other Multicast) and set each entry to 0.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* Multicast and Unicast packets are rejected.
* RETURN:
* None.
*/
-static void eth_port_init_mac_tables(unsigned int eth_port_num)
+static void eth_port_init_mac_tables(struct mv643xx_private *mp)
{
+ unsigned int port_num = mp->port_num;
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index <= 0xC; table_index += 4)
- mv_write(DA_FILTER_UNICAST_TABLE_BASE
- (eth_port_num) + table_index, 0);
+ wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
+ table_index, 0);
for (table_index = 0; table_index <= 0xFC; table_index += 4) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
- mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
- (eth_port_num) + table_index, 0);
+ wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
+ table_index, 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
- mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
- (eth_port_num) + table_index, 0);
+ wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
+ table_index, 0);
}
}
* A read from the MIB counter will reset the counter.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* After reading all MIB counters, the counters resets.
* MIB counter value.
*
*/
-static void eth_clear_mib_counters(unsigned int eth_port_num)
+static void eth_clear_mib_counters(struct mv643xx_private *mp)
{
+ unsigned int port_num = mp->port_num;
int i;
/* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4)
- mv_read(MIB_COUNTERS_BASE(eth_port_num) + i);
+ rdl(mp, MIB_COUNTERS_BASE(port_num) + i);
}
static inline u32 read_mib(struct mv643xx_private *mp, int offset)
{
- return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset);
+ return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset);
}
static void eth_update_mib_counters(struct mv643xx_private *mp)
* the specified port.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* None
* -ENODEV on failure
*
*/
-static int ethernet_phy_detect(unsigned int port_num)
+static int ethernet_phy_detect(struct mv643xx_private *mp)
{
unsigned int phy_reg_data0;
int auto_neg;
- eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
+ eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
auto_neg = phy_reg_data0 & 0x1000;
phy_reg_data0 ^= 0x1000; /* invert auto_neg */
- eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
+ eth_port_write_smi_reg(mp, 0, phy_reg_data0);
- eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
+ eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
if ((phy_reg_data0 & 0x1000) == auto_neg)
return -ENODEV; /* change didn't take */
phy_reg_data0 ^= 0x1000;
- eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
+ eth_port_write_smi_reg(mp, 0, phy_reg_data0);
return 0;
}
* This routine returns the given ethernet port PHY address.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* None.
* PHY address.
*
*/
-static int ethernet_phy_get(unsigned int eth_port_num)
+static int ethernet_phy_get(struct mv643xx_private *mp)
{
unsigned int reg_data;
- reg_data = mv_read(PHY_ADDR_REG);
+ reg_data = rdl(mp, PHY_ADDR_REG);
- return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+ return ((reg_data >> (5 * mp->port_num)) & 0x1f);
}
/*
* This routine sets the given ethernet port PHY address.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
* int phy_addr PHY address.
*
* OUTPUT:
* None.
*
*/
-static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
+static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
{
u32 reg_data;
- int addr_shift = 5 * eth_port_num;
+ int addr_shift = 5 * mp->port_num;
- reg_data = mv_read(PHY_ADDR_REG);
+ reg_data = rdl(mp, PHY_ADDR_REG);
reg_data &= ~(0x1f << addr_shift);
reg_data |= (phy_addr & 0x1f) << addr_shift;
- mv_write(PHY_ADDR_REG, reg_data);
+ wrl(mp, PHY_ADDR_REG, reg_data);
}
/*
* This routine utilizes the SMI interface to reset the ethernet port PHY.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* The PHY is reset.
* None.
*
*/
-static void ethernet_phy_reset(unsigned int eth_port_num)
+static void ethernet_phy_reset(struct mv643xx_private *mp)
{
unsigned int phy_reg_data;
/* Reset the PHY */
- eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
+ eth_port_read_smi_reg(mp, 0, &phy_reg_data);
phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
+ eth_port_write_smi_reg(mp, 0, phy_reg_data);
/* wait for PHY to come out of reset */
do {
udelay(1);
- eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
+ eth_port_read_smi_reg(mp, 0, &phy_reg_data);
} while (phy_reg_data & 0x8000);
}
-static void mv643xx_eth_port_enable_tx(unsigned int port_num,
+static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
unsigned int queues)
{
- mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
+ wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues);
}
-static void mv643xx_eth_port_enable_rx(unsigned int port_num,
+static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
unsigned int queues)
{
- mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
+ wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
}
-static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
+static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
{
+ unsigned int port_num = mp->port_num;
u32 queues;
/* Stop Tx port activity. Check port Tx activity. */
- queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
+ queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
if (queues) {
/* Issue stop command for active queues only */
- mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
+ wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
/* Wait for all Tx activity to terminate. */
/* Check port cause register that all Tx queues are stopped */
- while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
+ while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
udelay(PHY_WAIT_MICRO_SECONDS);
/* Wait for Tx FIFO to empty */
- while (mv_read(PORT_STATUS_REG(port_num)) &
+ while (rdl(mp, PORT_STATUS_REG(port_num)) &
ETH_PORT_TX_FIFO_EMPTY)
udelay(PHY_WAIT_MICRO_SECONDS);
}
return queues;
}
-static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
+static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
{
+ unsigned int port_num = mp->port_num;
u32 queues;
/* Stop Rx port activity. Check port Rx activity. */
- queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
+ queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
if (queues) {
/* Issue stop command for active queues only */
- mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
+ wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
/* Wait for all Rx activity to terminate. */
/* Check port cause register that all Rx queues are stopped */
- while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
+ while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
udelay(PHY_WAIT_MICRO_SECONDS);
}
* idle state after this command is performed and the port is disabled.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
*
* OUTPUT:
* Channel activity is halted.
* None.
*
*/
-static void eth_port_reset(unsigned int port_num)
+static void eth_port_reset(struct mv643xx_private *mp)
{
+ unsigned int port_num = mp->port_num;
unsigned int reg_data;
- mv643xx_eth_port_disable_tx(port_num);
- mv643xx_eth_port_disable_rx(port_num);
+ mv643xx_eth_port_disable_tx(mp);
+ mv643xx_eth_port_disable_rx(mp);
/* Clear all MIB counters */
- eth_clear_mib_counters(port_num);
+ eth_clear_mib_counters(mp);
/* Reset the Enable bit in the Configuration Register */
- reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
+ reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
reg_data &= ~(SERIAL_PORT_ENABLE |
DO_NOT_FORCE_LINK_FAIL |
FORCE_LINK_PASS);
- mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data);
+ wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
}
* order to perform PHY register read.
*
* INPUT:
- * unsigned int port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
* unsigned int phy_reg PHY register address offset.
* unsigned int *value Register value buffer.
*
* true otherwise.
*
*/
-static void eth_port_read_smi_reg(unsigned int port_num,
+static void eth_port_read_smi_reg(struct mv643xx_private *mp,
unsigned int phy_reg, unsigned int *value)
{
- int phy_addr = ethernet_phy_get(port_num);
+ int phy_addr = ethernet_phy_get(mp);
unsigned long flags;
int i;
spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
/* wait for the SMI register to become available */
- for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
+ for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
if (i == PHY_WAIT_ITERATIONS) {
- printk("mv643xx PHY busy timeout, port %d\n", port_num);
+ printk("%s: PHY busy timeout\n", mp->dev->name);
goto out;
}
udelay(PHY_WAIT_MICRO_SECONDS);
}
- mv_write(SMI_REG,
+ wrl(mp, SMI_REG,
(phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
/* now wait for the data to be valid */
- for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) {
+ for (i = 0; !(rdl(mp, SMI_REG) & ETH_SMI_READ_VALID); i++) {
if (i == PHY_WAIT_ITERATIONS) {
- printk("mv643xx PHY read timeout, port %d\n", port_num);
+ printk("%s: PHY read timeout\n", mp->dev->name);
goto out;
}
udelay(PHY_WAIT_MICRO_SECONDS);
}
- *value = mv_read(SMI_REG) & 0xffff;
+ *value = rdl(mp, SMI_REG) & 0xffff;
out:
spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
}
* order to perform writes to PHY registers.
*
* INPUT:
- * unsigned int eth_port_num Ethernet Port number.
+ * struct mv643xx_private *mp Ethernet Port.
* unsigned int phy_reg PHY register address offset.
* unsigned int value Register value.
*
* true otherwise.
*
*/
-static void eth_port_write_smi_reg(unsigned int eth_port_num,
+static void eth_port_write_smi_reg(struct mv643xx_private *mp,
unsigned int phy_reg, unsigned int value)
{
int phy_addr;
int i;
unsigned long flags;
- phy_addr = ethernet_phy_get(eth_port_num);
+ phy_addr = ethernet_phy_get(mp);
/* the SMI register is a shared resource */
spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
/* wait for the SMI register to become available */
- for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
+ for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
if (i == PHY_WAIT_ITERATIONS) {
- printk("mv643xx PHY busy timeout, port %d\n",
- eth_port_num);
+ printk("%s: PHY busy timeout\n", mp->dev->name);
goto out;
}
udelay(PHY_WAIT_MICRO_SECONDS);
}
- mv_write(SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
+ wrl(mp, SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
ETH_SMI_OPCODE_WRITE | (value & 0xffff));
out:
spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
*/
static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
{
- int val;
struct mv643xx_private *mp = netdev_priv(dev);
+ int val;
- eth_port_read_smi_reg(mp->port_num, location, &val);
+ eth_port_read_smi_reg(mp, location, &val);
return val;
}
static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
{
struct mv643xx_private *mp = netdev_priv(dev);
- eth_port_write_smi_reg(mp->port_num, location, val);
+ eth_port_write_smi_reg(mp, location, val);
}
/*
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff