#include <linux/platform_device.h>
#include <linux/phy.h>
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
#include "macb.h"
addr[4] = top & 0xff;
addr[5] = (top >> 8) & 0xff;
- if (is_valid_ether_addr(addr))
+ if (is_valid_ether_addr(addr)) {
memcpy(bp->dev->dev_addr, addr, sizeof(addr));
+ } else {
+ dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
+ random_ether_addr(bp->dev->dev_addr);
+ }
}
static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
}
if (phydev->link != bp->link) {
- if (phydev->link)
- netif_schedule(dev);
- else {
+ if (!phydev->link) {
bp->speed = 0;
bp->duplex = -1;
}
/* find the first phy */
for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
- if (bp->mii_bus.phy_map[phy_addr]) {
- phydev = bp->mii_bus.phy_map[phy_addr];
+ if (bp->mii_bus->phy_map[phy_addr]) {
+ phydev = bp->mii_bus->phy_map[phy_addr];
break;
}
}
/* Enable managment port */
macb_writel(bp, NCR, MACB_BIT(MPE));
- bp->mii_bus.name = "MACB_mii_bus";
- bp->mii_bus.read = &macb_mdio_read;
- bp->mii_bus.write = &macb_mdio_write;
- bp->mii_bus.reset = &macb_mdio_reset;
- snprintf(bp->mii_bus.id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
- bp->mii_bus.priv = bp;
- bp->mii_bus.dev = &bp->dev->dev;
+ bp->mii_bus = mdiobus_alloc();
+ if (bp->mii_bus == NULL) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ bp->mii_bus->name = "MACB_mii_bus";
+ bp->mii_bus->read = &macb_mdio_read;
+ bp->mii_bus->write = &macb_mdio_write;
+ bp->mii_bus->reset = &macb_mdio_reset;
+ snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
+ bp->mii_bus->priv = bp;
+ bp->mii_bus->parent = &bp->dev->dev;
pdata = bp->pdev->dev.platform_data;
if (pdata)
- bp->mii_bus.phy_mask = pdata->phy_mask;
+ bp->mii_bus->phy_mask = pdata->phy_mask;
- bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
- if (!bp->mii_bus.irq) {
+ bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
+ if (!bp->mii_bus->irq) {
err = -ENOMEM;
- goto err_out;
+ goto err_out_free_mdiobus;
}
for (i = 0; i < PHY_MAX_ADDR; i++)
- bp->mii_bus.irq[i] = PHY_POLL;
+ bp->mii_bus->irq[i] = PHY_POLL;
- platform_set_drvdata(bp->dev, &bp->mii_bus);
+ platform_set_drvdata(bp->dev, bp->mii_bus);
- if (mdiobus_register(&bp->mii_bus))
+ if (mdiobus_register(bp->mii_bus))
goto err_out_free_mdio_irq;
if (macb_mii_probe(bp->dev) != 0) {
return 0;
err_out_unregister_bus:
- mdiobus_unregister(&bp->mii_bus);
+ mdiobus_unregister(bp->mii_bus);
err_out_free_mdio_irq:
- kfree(bp->mii_bus.irq);
+ kfree(bp->mii_bus->irq);
+err_out_free_mdiobus:
+ mdiobus_free(bp->mii_bus);
err_out:
return err;
}
printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
bp->dev->name);
+ /* Transfer ongoing, disable transmitter, to avoid confusion */
+ if (status & MACB_BIT(TGO))
+ macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
+
head = bp->tx_head;
/*Mark all the buffer as used to avoid sending a lost buffer*/
}
bp->tx_head = bp->tx_tail = 0;
+
+ /* Enable the transmitter again */
+ if (status & MACB_BIT(TGO))
+ macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
}
if (!(status & MACB_BIT(COMP)))
bp->stats.rx_packets++;
bp->stats.rx_bytes += len;
- bp->dev->last_rx = jiffies;
dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
skb->len, skb->csum);
netif_receive_skb(skb);
* this function was called last time, and no packets
* have been received since.
*/
- netif_rx_complete(dev, napi);
+ netif_rx_complete(napi);
goto out;
}
dev_warn(&bp->pdev->dev,
"No RX buffers complete, status = %02lx\n",
(unsigned long)status);
- netif_rx_complete(dev, napi);
+ netif_rx_complete(napi);
goto out;
}
work_done = macb_rx(bp, budget);
if (work_done < budget)
- netif_rx_complete(dev, napi);
+ netif_rx_complete(napi);
/*
* We've done what we can to clean the buffers. Make sure we
}
if (status & MACB_RX_INT_FLAGS) {
- if (netif_rx_schedule_prep(dev, &bp->napi)) {
+ if (netif_rx_schedule_prep(&bp->napi)) {
/*
* There's no point taking any more interrupts
* until we have processed the buffers
macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
dev_dbg(&bp->pdev->dev,
"scheduling RX softirq\n");
- __netif_rx_schedule(dev, &bp->napi);
+ __netif_rx_schedule(&bp->napi);
}
}
unsigned long pclk_hz;
u32 config;
int err = -ENXIO;
- DECLARE_MAC_BUF(mac);
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
platform_set_drvdata(pdev, dev);
- printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
- "(%s)\n",
- dev->name, dev->base_addr, dev->irq,
- print_mac(mac, dev->dev_addr));
+ printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
+ dev->name, dev->base_addr, dev->irq, dev->dev_addr);
phydev = bp->phy_dev;
printk(KERN_INFO "%s: attached PHY driver [%s] "
bp = netdev_priv(dev);
if (bp->phy_dev)
phy_disconnect(bp->phy_dev);
- mdiobus_unregister(&bp->mii_bus);
- kfree(bp->mii_bus.irq);
+ mdiobus_unregister(bp->mii_bus);
+ kfree(bp->mii_bus->irq);
+ mdiobus_free(bp->mii_bus);
unregister_netdev(dev);
free_irq(dev->irq, dev);
iounmap(bp->regs);
return 0;
}
+#ifdef CONFIG_PM
+static int macb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct net_device *netdev = platform_get_drvdata(pdev);
+ struct macb *bp = netdev_priv(netdev);
+
+ netif_device_detach(netdev);
+
+#ifndef CONFIG_ARCH_AT91
+ clk_disable(bp->hclk);
+#endif
+ clk_disable(bp->pclk);
+
+ return 0;
+}
+
+static int macb_resume(struct platform_device *pdev)
+{
+ struct net_device *netdev = platform_get_drvdata(pdev);
+ struct macb *bp = netdev_priv(netdev);
+
+ clk_enable(bp->pclk);
+#ifndef CONFIG_ARCH_AT91
+ clk_enable(bp->hclk);
+#endif
+
+ netif_device_attach(netdev);
+
+ return 0;
+}
+#else
+#define macb_suspend NULL
+#define macb_resume NULL
+#endif
+
static struct platform_driver macb_driver = {
.remove = __exit_p(macb_remove),
+ .suspend = macb_suspend,
+ .resume = macb_resume,
.driver = {
.name = "macb",
+ .owner = THIS_MODULE,
},
};
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
+MODULE_ALIAS("platform:macb");