for (i = 0; i < dma->num_pages; i++) {
if (dma->pg_arr[i]) {
- pci_free_consistent(dev->pcidev, BCM_PAGE_SIZE,
- dma->pg_arr[i], dma->pg_map_arr[i]);
+ dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
+ dma->pg_arr[i], dma->pg_map_arr[i]);
dma->pg_arr[i] = NULL;
}
}
if (dma->pgtbl) {
- pci_free_consistent(dev->pcidev, dma->pgtbl_size,
- dma->pgtbl, dma->pgtbl_map);
+ dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
+ dma->pgtbl, dma->pgtbl_map);
dma->pgtbl = NULL;
}
kfree(dma->pg_arr);
dma->num_pages = pages;
for (i = 0; i < pages; i++) {
- dma->pg_arr[i] = pci_alloc_consistent(dev->pcidev,
- BCM_PAGE_SIZE,
- &dma->pg_map_arr[i]);
+ dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
+ BCM_PAGE_SIZE,
+ &dma->pg_map_arr[i],
+ GFP_ATOMIC);
if (dma->pg_arr[i] == NULL)
goto error;
}
dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
~(BCM_PAGE_SIZE - 1);
- dma->pgtbl = pci_alloc_consistent(dev->pcidev, dma->pgtbl_size,
- &dma->pgtbl_map);
+ dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
+ &dma->pgtbl_map, GFP_ATOMIC);
if (dma->pgtbl == NULL)
goto error;
for (i = 0; i < cp->ctx_blks; i++) {
if (cp->ctx_arr[i].ctx) {
- pci_free_consistent(dev->pcidev, cp->ctx_blk_size,
- cp->ctx_arr[i].ctx,
- cp->ctx_arr[i].mapping);
+ dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
+ cp->ctx_arr[i].ctx,
+ cp->ctx_arr[i].mapping);
cp->ctx_arr[i].ctx = NULL;
}
}
}
if (cp->l2_buf) {
- pci_free_consistent(dev->pcidev, cp->l2_buf_size,
- cp->l2_buf, cp->l2_buf_map);
+ dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
+ cp->l2_buf, cp->l2_buf_map);
cp->l2_buf = NULL;
}
if (cp->l2_ring) {
- pci_free_consistent(dev->pcidev, cp->l2_ring_size,
- cp->l2_ring, cp->l2_ring_map);
+ dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
+ cp->l2_ring, cp->l2_ring_map);
cp->l2_ring = NULL;
}
for (i = 0; i < cp->ctx_blks; i++) {
cp->ctx_arr[i].ctx =
- pci_alloc_consistent(dev->pcidev, BCM_PAGE_SIZE,
- &cp->ctx_arr[i].mapping);
+ dma_alloc_coherent(&dev->pcidev->dev,
+ BCM_PAGE_SIZE,
+ &cp->ctx_arr[i].mapping,
+ GFP_KERNEL);
if (cp->ctx_arr[i].ctx == NULL)
return -ENOMEM;
}
struct cnic_local *cp = dev->cnic_priv;
cp->l2_ring_size = pages * BCM_PAGE_SIZE;
- cp->l2_ring = pci_alloc_consistent(dev->pcidev, cp->l2_ring_size,
- &cp->l2_ring_map);
+ cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
+ &cp->l2_ring_map,
+ GFP_KERNEL | __GFP_COMP);
if (!cp->l2_ring)
return -ENOMEM;
cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
- cp->l2_buf = pci_alloc_consistent(dev->pcidev, cp->l2_buf_size,
- &cp->l2_buf_map);
+ cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
+ &cp->l2_buf_map,
+ GFP_KERNEL | __GFP_COMP);
if (!cp->l2_buf)
return -ENOMEM;
for (i = 0; i < blks; i++) {
cp->ctx_arr[i].ctx =
- pci_alloc_consistent(dev->pcidev, cp->ctx_blk_size,
- &cp->ctx_arr[i].mapping);
+ dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
+ &cp->ctx_arr[i].mapping,
+ GFP_KERNEL);
if (cp->ctx_arr[i].ctx == NULL)
return -ENOMEM;
cp->bnx2x_status_blk = cp->status_blk;
cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
+ memset(cp->bnx2x_status_blk, 0, sizeof(struct host_status_block));
+
cp->l2_rx_ring_size = 15;
ret = cnic_alloc_l2_rings(dev, 4);
ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
ictx->ustorm_st_context.ring.rq.pbl_base.lo =
- req2->rq_page_table_addr_lo & 0xffffffff;
+ req2->rq_page_table_addr_lo;
ictx->ustorm_st_context.ring.rq.pbl_base.hi =
- (u64) req2->rq_page_table_addr_hi >> 32;
+ req2->rq_page_table_addr_hi;
ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
if (base < 0xa0000 || base >= 0xc0000)
return;
- val = BNX2X_SHMEM_ADDR(base,
+ addr = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_upper);
+ val = CNIC_RD(dev, addr);
+
dev->mac_addr[0] = (u8) (val >> 8);
dev->mac_addr[1] = (u8) val;
- val = BNX2X_SHMEM_ADDR(base,
+ addr = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_lower);
+ val = CNIC_RD(dev, addr);
+
dev->mac_addr[2] = (u8) (val >> 24);
dev->mac_addr[3] = (u8) (val >> 16);
dev->mac_addr[4] = (u8) (val >> 8);
cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
msleep(10);
+
+ memset(&l5_data, 0, sizeof(l5_data));
+ cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
+ BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
+ (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
+ msleep(10);
}
}
offsetof(struct cstorm_status_block_c,
index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
0);
+ CNIC_WR(dev, BAR_CSTRORM_INTMEM +
+ CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
+ CNIC_WR16(dev, cp->kcq_io_addr, 0);
cnic_free_resc(dev);
}