usbnet: ratelimit warning messages invoked from callback handler

[safe/jmp/linux-2.6] / drivers / net / bnx2x_reg.h

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index d3086e9..b8ce6fc 100644 (file)
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -5239,6 +5239,7 @@
 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK                         3
 #define HW_LOCK_RESOURCE_SPIO                                   2
 #define HW_LOCK_RESOURCE_UNDI                                   5
+#define PRS_FLAG_OVERETH_IPV4                                   1
 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR                (1<<18)
 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT                (1<<31)
 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT                (1<<9)
@@ -5409,7 +5410,7 @@
 #define PCICFG_COMMAND_INT_DISABLE             (1<<10)
 #define PCICFG_COMMAND_RESERVED                (0x1f<<11)
 #define PCICFG_STATUS_OFFSET                           0x06
-#define PCICFG_REVESION_ID                             0x08
+#define PCICFG_REVESION_ID_OFFSET                      0x08
 #define PCICFG_CACHE_LINE_SIZE                         0x0c
 #define PCICFG_LATENCY_TIMER                           0x0d
 #define PCICFG_BAR_1_LOW                               0x10
@@ -5437,7 +5438,7 @@
 #define PCICFG_PM_CSR_STATE                    (0x3<<0)
 #define PCICFG_PM_CSR_PME_ENABLE               (1<<8)
 #define PCICFG_PM_CSR_PME_STATUS               (1<<15)
-#define PCICFG_MSI_CAP_ID                              0x58
+#define PCICFG_MSI_CAP_ID_OFFSET                       0x58
 #define PCICFG_MSI_CONTROL_ENABLE              (0x1<<16)
 #define PCICFG_MSI_CONTROL_MCAP                (0x7<<17)
 #define PCICFG_MSI_CONTROL_MENA                (0x7<<20)
@@ -5445,7 +5446,7 @@
 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE  (0x1<<24)
 #define PCICFG_GRC_ADDRESS                             0x78
 #define PCICFG_GRC_DATA                                0x80
-#define PCICFG_MSIX_CAP_ID                             0xa0
+#define PCICFG_MSIX_CAP_ID_OFFSET                      0xa0
 #define PCICFG_MSIX_CONTROL_TABLE_SIZE         (0x7ff<<16)
 #define PCICFG_MSIX_CONTROL_RESERVED           (0x7<<27)
 #define PCICFG_MSIX_CONTROL_FUNC_MASK          (0x1<<30)
@@ -5603,6 +5604,42 @@
 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
 #define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
 
+#define MDIO_REG_BANK_TX1                              0x8070
+#define MDIO_TX1_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_TX2                              0x8080
+#define MDIO_TX2_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
+#define MDIO_REG_BANK_TX3                              0x8090
+#define MDIO_TX3_TX_DRIVER                             0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK            0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT           12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT               8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK             0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT            4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK               0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT              1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T                     1
+
 #define MDIO_REG_BANK_XGXS_BLOCK0                      0x8000
 #define MDIO_BLOCK0_XGXS_CONTROL                       0x10
 
@@ -5806,6 +5843,7 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_ROM_VER2          0xca1a
 #define MDIO_PMA_REG_EDC_FFE_MAIN      0xca1b
 #define MDIO_PMA_REG_PLL_BANDWIDTH     0xca1d
+#define MDIO_PMA_REG_GEN_CTRL2         0xca1e
 #define MDIO_PMA_REG_MISC_CTRL0        0xca23
 #define MDIO_PMA_REG_LRM_MODE          0xca3f
 #define MDIO_PMA_REG_CDR_BANDWIDTH     0xca46
@@ -5825,6 +5863,10 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_8726_TX_CTRL2             0xca05
 
 
+#define MDIO_PMA_REG_8073_CHIP_REV                     0xc801
+#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS            0xc820
+#define MDIO_PMA_REG_8073_XAUI_WA                      0xc841
+
 #define MDIO_PMA_REG_7101_RESET        0xc000
 #define MDIO_PMA_REG_7107_LED_CNTL     0xc007
 #define MDIO_PMA_REG_7101_VER1         0xc026
@@ -5881,6 +5923,8 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_AN_REG_CL37_FC_LD         0xffe4
 #define MDIO_AN_REG_CL37_FC_LP         0xffe5
 
+#define MDIO_AN_REG_8073_2_5G          0x8329
+
 
 #define IGU_FUNC_BASE                  0x0400