pci: Add SR-IOV convenience functions and macros

[safe/jmp/linux-2.6] / drivers / net / bnx2x_reg.h

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index aa76cba..944964e 100644 (file)
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -2536,7 +2536,7 @@
 /* [RC 1] A flag to indicate that overflow error occurred in one of the
    queues. */
 #define QM_REG_OVFERROR                                         0x16805c
-/* [RC 7] the Q were the qverflow occurs */
+/* [RC 7] the Q where the overflow occurs */
 #define QM_REG_OVFQNUM                                          0x168058
 /* [R 16] Pause state for physical queues 15-0 */
 #define QM_REG_PAUSESTATE0                                      0x168410
@@ -4772,18 +4772,28 @@
 #define PCI_ID_VAL2                                    0x438
 
 
-#define MDIO_REG_BANK_CL73_IEEEB0                      0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL               0x0
+#define MDIO_REG_BANK_CL73_IEEEB0      0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL       0x0
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN    0x0200
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN         0x1000
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST      0x8000
 
-#define MDIO_REG_BANK_CL73_IEEEB1                      0x10
-#define MDIO_CL73_IEEEB1_AN_ADV2                               0x01
+#define MDIO_REG_BANK_CL73_IEEEB1      0x10
+#define MDIO_CL73_IEEEB1_AN_ADV1               0x00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE                 0x0400
+#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC            0x0800
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH            0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK            0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV2               0x01
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M            0x0000
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX         0x0020
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4          0x0040
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR           0x0080
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1            0x03
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE              0x0400
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC         0x0800
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH         0x0C00
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK         0x0C00
 
 #define MDIO_REG_BANK_RX0                              0x80b0
 #define MDIO_RX0_RX_STATUS                             0x10
@@ -4910,6 +4920,8 @@
 
 
 #define MDIO_REG_BANK_10G_PARALLEL_DETECT              0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS            0x10
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK            0x8000
 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL           0x11
 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN      0x1
 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK              0x13
@@ -4934,6 +4946,8 @@
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G                   0x0010
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M                 0x0008
 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M                  0x0000
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2                    0x15
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED                0x0002
 #define MDIO_SERDES_DIGITAL_MISC1                              0x18
 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK                      0xE000
 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M                       0x0000
@@ -5115,6 +5129,7 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_8481_LED1_MASK    0xa82c
 #define MDIO_PMA_REG_8481_LED2_MASK    0xa82f
 #define MDIO_PMA_REG_8481_LED3_MASK    0xa832
+#define MDIO_PMA_REG_8481_LED3_BLINK   0xa834
 #define MDIO_PMA_REG_8481_SIGNAL_MASK  0xa835
 #define MDIO_PMA_REG_8481_LINK_SIGNAL  0xa83b