* the Free Software Foundation.
*/
+struct license_key {
+ u32 reserved[6];
+
+#if defined(__BIG_ENDIAN)
+ u16 max_iscsi_init_conn;
+ u16 max_iscsi_trgt_conn;
+#elif defined(__LITTLE_ENDIAN)
+ u16 max_iscsi_trgt_conn;
+ u16 max_iscsi_init_conn;
+#endif
+
+ u32 reserved_a[6];
+};
+
#define PORT_0 0
#define PORT_1 1
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
+#define DRV_MSG_CODE_DCC_OK 0x30000000
+#define DRV_MSG_CODE_DCC_FAILURE 0x31000000
#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
+#define FW_MSG_CODE_DCC_DONE 0x30100000
#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
u32 drv_status;
#define DRV_STATUS_PMF 0x00000001
+#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
+#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
+#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
+#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
+#define DRV_STATUS_DCC_RESERVED1 0x00000800
+#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
+#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
+
u32 virt_mac_upper;
#define VIRT_MAC_SIGN_MASK 0xffff0000
#define VIRT_MAC_SIGNATURE 0x564d0000
struct port_mf_cfg {
u32 dynamic_cfg; /* device control channel */
-#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
-#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
-#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
-#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
+#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
+#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
+#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
u32 reserved[3];
struct shm_dev_info dev_info; /* 0x8 (0x438) */
- u8 reserved[52*PORT_MAX];
+ struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
/* FW information (for internal FW use) */
u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
}; /* 0x6dc */
+struct shmem2_region {
+
+ u32 size;
+
+ u32 dcc_support;
+#define SHMEM_DCC_SUPPORT_NONE 0x00000000
+#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
+#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
+#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
+#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
+#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
+#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
+
+};
+
+
struct emac_stats {
u32 rx_stat_ifhcinoctets;
u32 rx_stat_ifhcinbadoctets;
#define BCM_5710_FW_MAJOR_VERSION 5
-#define BCM_5710_FW_MINOR_VERSION 0
-#define BCM_5710_FW_REVISION_VERSION 21
+#define BCM_5710_FW_MINOR_VERSION 2
+#define BCM_5710_FW_REVISION_VERSION 7
#define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1