#endif
};
+/*
+ * status_block definition
+ */
+struct status_block_msix {
+#if defined(__BIG_ENDIAN)
+ u16 status_tx_quick_consumer_index;
+ u16 status_rx_quick_consumer_index;
+ u16 status_completion_producer_index;
+ u16 status_cmd_consumer_index;
+ u32 status_unused;
+ u16 status_idx;
+ u8 status_unused2;
+ u8 status_blk_num;
+#elif defined(__LITTLE_ENDIAN)
+ u16 status_rx_quick_consumer_index;
+ u16 status_tx_quick_consumer_index;
+ u16 status_cmd_consumer_index;
+ u16 status_completion_producer_index;
+ u32 status_unused;
+ u8 status_blk_num;
+ u8 status_unused2;
+ u16 status_idx;
+#endif
+};
+
+#define BNX2_SBLK_MSIX_ALIGN_SIZE 128
+
/*
* statistics_block definition
#define BNX2_L2CTX_BD_PRE_READ 0x00000000
#define BNX2_L2CTX_CTX_SIZE 0x00000000
#define BNX2_L2CTX_CTX_TYPE 0x00000000
+#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 32
+#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4
+#define BNX2_L2CTX_LO_WATER_MARK_DIS 0
+#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4
+#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16
+#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff
#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
#define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24)
+#define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT 24
#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
#define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13)
#define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31)
+#define BNX2_PCI_GRC_WINDOW2_BASE 0xc000
+#define BNX2_PCI_GRC_WINDOW3_BASE 0xe000
+
#define BNX2_PCI_CONFIG_1 0x00000404
#define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0)
#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
#define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618
#define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13)
+#define BNX2_MSIX_TABLE_ADDR 0x318000
+#define BNX2_MSIX_PBA_ADDR 0x31c000
/*
* misc_reg definition
#define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31)
#define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646
+#define BNX2_MQ_MAP_L2_5 0x00003d34
+#define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26)
+
/*
* tsch_reg definition
* offset: 0x4c00
#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
+#define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \
+ BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
+ BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+
/*
* txp_reg definition
#define MII_BNX2_DSP_RW_PORT 0x15
#define MII_BNX2_DSP_ADDRESS 0x17
#define MII_BNX2_DSP_EXPAND_REG 0x0f00
+#define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1)
+#define MII_EXPAND_REG1_RUDI_C 0x20
+#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3)
+
+#define MII_BNX2_MISC_SHADOW 0x1c
+#define MISC_SHDW_AN_DBG 0x6800
+#define MISC_SHDW_AN_DBG_NOSYNC 0x0002
+#define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100
+#define MISC_SHDW_MODE_CTL 0x7c00
+#define MISC_SHDW_MODE_CTL_SIG_DET 0x0010
#define MII_BNX2_BLK_ADDR 0x1f
#define MII_BNX2_BLK_ADDR_IEEE0 0x0000
#define RX_COPY_THRESH 128
-#define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff
+#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff
#define DMA_READ_CHANS 5
#define DMA_WRITE_CHANS 3
u8 *name;
};
+#define BNX2_MAX_MSIX_HW_VEC 9
+#define BNX2_MAX_MSIX_VEC 2
+#define BNX2_BASE_VEC 0
+#define BNX2_TX_VEC 1
+#define BNX2_TX_INT_NUM (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
+
+struct bnx2_irq {
+ irq_handler_t handler;
+ u16 vector;
+ u8 requested;
+ char name[16];
+};
+
+struct bnx2_napi {
+ struct napi_struct napi ____cacheline_aligned;
+ struct bnx2 *bp;
+ struct status_block *status_blk;
+ struct status_block_msix *status_blk_msix;
+ u32 last_status_idx;
+ u32 int_num;
+
+ u16 tx_cons;
+ u16 hw_tx_cons;
+
+ u32 rx_prod_bseq;
+ u16 rx_prod;
+ u16 rx_cons;
+
+ u16 rx_pg_prod;
+ u16 rx_pg_cons;
+
+};
+
struct bnx2 {
/* Fields used in the tx and intr/napi performance paths are grouped */
/* together in the beginning of the structure. */
struct net_device *dev;
struct pci_dev *pdev;
- struct napi_struct napi;
-
atomic_t intr_sem;
- struct status_block *status_blk;
- u32 last_status_idx;
-
u32 flags;
-#define PCIX_FLAG 0x00000001
-#define PCI_32BIT_FLAG 0x00000002
-#define ONE_TDMA_FLAG 0x00000004 /* no longer used */
-#define NO_WOL_FLAG 0x00000008
-#define USING_MSI_FLAG 0x00000020
-#define ASF_ENABLE_FLAG 0x00000040
-#define MSI_CAP_FLAG 0x00000080
-#define ONE_SHOT_MSI_FLAG 0x00000100
-#define PCIE_FLAG 0x00000200
+#define BNX2_FLAG_PCIX 0x00000001
+#define BNX2_FLAG_PCI_32BIT 0x00000002
+#define BNX2_FLAG_MSIX_CAP 0x00000004
+#define BNX2_FLAG_NO_WOL 0x00000008
+#define BNX2_FLAG_USING_MSI 0x00000020
+#define BNX2_FLAG_ASF_ENABLE 0x00000040
+#define BNX2_FLAG_MSI_CAP 0x00000080
+#define BNX2_FLAG_ONE_SHOT_MSI 0x00000100
+#define BNX2_FLAG_PCIE 0x00000200
+#define BNX2_FLAG_USING_MSIX 0x00000400
+#define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \
+ BNX2_FLAG_USING_MSIX)
+#define BNX2_FLAG_JUMBO_BROKEN 0x00000800
/* Put tx producer and consumer fields in separate cache lines. */
u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
u16 tx_prod;
+ u8 tx_vec;
u32 tx_bidx_addr;
u32 tx_bseq_addr;
- u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
- u16 hw_tx_cons;
+ struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC];
#ifdef BCM_VLAN
struct vlan_group *vlgrp;
u32 rx_max_ring_idx;
u32 rx_max_pg_ring_idx;
- u32 rx_prod_bseq;
- u16 rx_prod;
- u16 rx_cons;
-
- u16 rx_pg_prod;
- u16 rx_pg_cons;
-
u32 rx_csum;
struct sw_bd *rx_buf_ring;
spinlock_t indirect_lock;
u32 phy_flags;
-#define PHY_SERDES_FLAG 1
-#define PHY_CRC_FIX_FLAG 2
-#define PHY_PARALLEL_DETECT_FLAG 4
-#define PHY_2_5G_CAPABLE_FLAG 8
-#define PHY_INT_MODE_MASK_FLAG 0x300
-#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
-#define PHY_INT_MODE_LINK_READY_FLAG 0x200
-#define PHY_DIS_EARLY_DAC_FLAG 0x400
-#define REMOTE_PHY_CAP_FLAG 0x800
+#define BNX2_PHY_FLAG_SERDES 0x00000001
+#define BNX2_PHY_FLAG_CRC_FIX 0x00000002
+#define BNX2_PHY_FLAG_PARALLEL_DETECT 0x00000004
+#define BNX2_PHY_FLAG_2_5G_CAPABLE 0x00000008
+#define BNX2_PHY_FLAG_INT_MODE_MASK 0x00000300
+#define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING 0x00000100
+#define BNX2_PHY_FLAG_INT_MODE_LINK_READY 0x00000200
+#define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400
+#define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800
+#define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000
+#define BNX2_PHY_FLAG_NO_PARALLEL 0x00002000
u32 mii_bmcr;
u32 mii_bmsr;
u32 stats_ticks;
+ struct status_block *status_blk;
dma_addr_t status_blk_mapping;
struct statistics_block *stats_blk;
u32 flash_size;
int status_stats_size;
-};
-static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
-static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
+ struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC];
+ int irq_nvecs;
+};
#define REG_RD(bp, offset) \
readl(bp->regview + offset)
#define REG_WR16(bp, offset, val) \
writew(val, bp->regview + offset)
-#define REG_RD_IND(bp, offset) \
- bnx2_reg_rd_ind(bp, offset)
-
-#define REG_WR_IND(bp, offset, val) \
- bnx2_reg_wr_ind(bp, offset, val)
-
-/* Indirect context access. Unlike the MBQ_WR, these macros will not
- * trigger a chip event. */
-static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
-
-#define CTX_WR(bp, cid_addr, offset, val) \
- bnx2_ctx_wr(bp, cid_addr, offset, val)
-
struct cpu_reg {
u32 mode;
u32 mode_value_halt;
const u32 text_addr;
const u32 text_len;
const u32 text_index;
- u32 *text;
+ __le32 *text;
u8 *gz_text;
const u32 gz_text_len;
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff