cpumask: sh: Introduce cpumask_of_{node,pcibus} to replace {node,pcibus}_to_cpumask

[safe/jmp/linux-2.6] / drivers / net / bnx2.h

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 1c5ce80..0b032c3 100644 (file)
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -378,6 +378,9 @@ struct l2_fhdr {
  *  pci_config_l definition
  *  offset: 0000
  */
+#define BNX2_PCICFG_MSI_CONTROL                                0x00000058
+#define BNX2_PCICFG_MSI_CONTROL_ENABLE                  (1L<<16)
+
 #define BNX2_PCICFG_MISC_CONFIG                                0x00000068
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP        (1L<<2)
 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP     (1L<<3)
@@ -4158,6 +4161,23 @@ struct l2_fhdr {
 
 
 /*
+ *  rlup_reg definition
+ *  offset: 0x2000
+ */
+#define BNX2_RLUP_RSS_CONFIG                           0x0000201c
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI           (0x3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI       (0L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI       (1L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI   (2L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI       (3L<<0)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI           (0x3L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI       (0L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI       (1L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI   (2L<<2)
+#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI       (3L<<2)
+
+
+/*
  *  rbuf_reg definition
  *  offset: 0x200000
  */
@@ -5528,6 +5548,9 @@ struct l2_fhdr {
 #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
                                         BNX2_HC_SB_CONFIG_1)
 #define BNX2_HC_TX_TICKS_OFF   (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_OFF (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
+                                        BNX2_HC_SB_CONFIG_1)
+#define BNX2_HC_RX_TICKS_OFF   (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
 
 
 /*
@@ -5856,6 +5879,9 @@ struct l2_fhdr {
 #define BNX2_RXP_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
 
 #define BNX2_RXP_SCRATCH                               0x000e0000
+#define BNX2_RXP_SCRATCH_RSS_TBL_SZ                     0x000e0038
+#define BNX2_RXP_SCRATCH_RSS_TBL                        0x000e003c
+#define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES            128
 
 
 /*
@@ -6417,6 +6443,11 @@ struct l2_fhdr {
 
 #define BNX2_MISC_ENABLE_DEFAULT       0x17ffffff
 
+#define BNX2_START_UNICAST_ADDRESS_INDEX       4
+#define BNX2_END_UNICAST_ADDRESS_INDEX         7
+#define BNX2_MAX_UNICAST_ADDRESSES             (BNX2_END_UNICAST_ADDRESS_INDEX - \
+                                        BNX2_START_UNICAST_ADDRESS_INDEX + 1)
+
 #define DMA_READ_CHANS 5
 #define DMA_WRITE_CHANS        3
 
@@ -6480,6 +6511,10 @@ struct l2_fhdr {
 #define TX_TSS_CID     32
 #define RX_CID         0
 #define RX_RSS_CID     4
+#define RX_MAX_RSS_RINGS       7
+#define RX_MAX_RINGS           (RX_MAX_RSS_RINGS + 1)
+#define TX_MAX_TSS_RINGS       7
+#define TX_MAX_RINGS           (TX_MAX_TSS_RINGS + 1)
 
 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
@@ -6494,10 +6529,14 @@ struct sw_pg {
        DECLARE_PCI_UNMAP_ADDR(mapping)
 };
 
+struct sw_tx_bd {
+       struct sk_buff          *skb;
+};
+
 #define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT)
 #define SW_RXPG_RING_SIZE (sizeof(struct sw_pg) * RX_DESC_CNT)
 #define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
-#define SW_TXBD_RING_SIZE (sizeof(struct sw_bd) * TX_DESC_CNT)
+#define SW_TXBD_RING_SIZE (sizeof(struct sw_tx_bd) * TX_DESC_CNT)
 #define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 
 /* Buffered flash (Atmel: AT45DB011B) specific information */
@@ -6558,14 +6597,14 @@ struct flash_spec {
 };
 
 #define BNX2_MAX_MSIX_HW_VEC   9
-#define BNX2_MAX_MSIX_VEC      2
+#define BNX2_MAX_MSIX_VEC      9
 #define BNX2_BASE_VEC          0
 #define BNX2_TX_VEC            1
 #define BNX2_TX_INT_NUM        (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
 
 struct bnx2_irq {
        irq_handler_t   handler;
-       u16             vector;
+       unsigned int    vector;
        u8              requested;
        char            name[16];
 };
@@ -6577,7 +6616,7 @@ struct bnx2_tx_ring_info {
        u32                     tx_bseq_addr;
 
        struct tx_bd            *tx_desc_ring;
-       struct sw_bd            *tx_buf_ring;
+       struct sw_tx_bd         *tx_buf_ring;
 
        u16                     tx_cons;
        u16                     hw_tx_cons;
@@ -6609,8 +6648,12 @@ struct bnx2_rx_ring_info {
 struct bnx2_napi {
        struct napi_struct      napi            ____cacheline_aligned;
        struct bnx2             *bp;
-       struct status_block     *status_blk;
-       struct status_block_msix        *status_blk_msix;
+       union {
+               struct status_block             *msi;
+               struct status_block_msix        *msix;
+       } status_blk;
+       u16                     *hw_tx_cons_ptr;
+       u16                     *hw_rx_cons_ptr;
        u32                     last_status_idx;
        u32                     int_num;
 
@@ -6618,6 +6661,8 @@ struct bnx2_napi {
        struct bnx2_tx_ring_info        tx_ring;
 };
 
+#define BNX2_TIMER_INTERVAL                    HZ
+
 struct bnx2 {
        /* Fields used in the tx and intr/napi performance paths are grouped */
        /* together in the beginning of the structure. */
@@ -6642,6 +6687,7 @@ struct bnx2 {
 #define BNX2_FLAG_USING_MSI_OR_MSIX    (BNX2_FLAG_USING_MSI | \
                                         BNX2_FLAG_USING_MSIX)
 #define BNX2_FLAG_JUMBO_BROKEN         0x00000800
+#define BNX2_FLAG_CAN_KEEP_VLAN                0x00001000
 
        struct bnx2_napi        bnx2_napi[BNX2_MAX_MSIX_VEC];
 
@@ -6664,9 +6710,6 @@ struct bnx2 {
 
        /* End of fields used in the performance code paths. */
 
-       char                    *name;
-
-       int                     timer_interval;
        int                     current_interval;
        struct                  timer_list timer;
        struct work_struct      reset_task;
@@ -6759,7 +6802,6 @@ struct bnx2 {
 
        u32                     stats_ticks;
 
-       struct status_block     *status_blk;
        dma_addr_t              status_blk_mapping;
 
        struct statistics_block *stats_blk;
@@ -6824,6 +6866,9 @@ struct bnx2 {
 
        u8                      num_tx_rings;
        u8                      num_rx_rings;
+
+       u32                     idle_chk_status_idx;
+
 };
 
 #define REG_RD(bp, offset)                                     \
@@ -6924,6 +6969,7 @@ struct fw_info {
 #define BNX2_DRV_MSG_CODE_DIAG                  0x07000000
 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL        0x09000000
 #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN                 0x0b000000
+#define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE      0x0d000000
 #define BNX2_DRV_MSG_CODE_CMD_SET_LINK          0x10000000
 
 #define BNX2_DRV_MSG_DATA                       0x00ff0000
@@ -7252,6 +7298,10 @@ struct fw_info {
 #define BNX2_FW_CAP_SIGNATURE_MASK              0xffff0000
 #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE          0x00000001
 #define BNX2_FW_CAP_REMOTE_PHY_PRESENT          0x00000002
+#define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN           0x00000008
+#define BNX2_FW_CAP_BC_CAN_KEEP_VLAN            0x00000010
+#define BNX2_FW_CAP_CAN_KEEP_VLAN      (BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \
+                                        BNX2_FW_CAP_MFW_CAN_KEEP_VLAN)
 
 #define BNX2_RPHY_SIGNATURE                    0x36c
 #define BNX2_RPHY_LOAD_SIGNATURE                0x5a5a5a5a