EMAC driver: fix bug - invalidate data cache of new_skb->data range when cache is WB

[safe/jmp/linux-2.6] / drivers / net / bnx2.c

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 8e9fe48..8b552c6 100644 (file)
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -56,8 +56,8 @@
 
 #define DRV_MODULE_NAME                "bnx2"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "1.7.2"
-#define DRV_MODULE_RELDATE     "January 21, 2008"
+#define DRV_MODULE_VERSION     "1.7.3"
+#define DRV_MODULE_RELDATE     "January 29, 2008"
 
 #define RUN_AT(x) (jiffies + (x))
 
@@ -992,6 +992,42 @@ bnx2_copper_linkup(struct bnx2 *bp)
        return 0;
 }
 
+static void
+bnx2_init_rx_context0(struct bnx2 *bp)
+{
+       u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
+
+       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
+       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
+       val |= 0x02 << 8;
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               u32 lo_water, hi_water;
+
+               if (bp->flow_ctrl & FLOW_CTRL_TX)
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
+               else
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
+               if (lo_water >= bp->rx_ring_size)
+                       lo_water = 0;
+
+               hi_water = bp->rx_ring_size / 4;
+
+               if (hi_water <= lo_water)
+                       lo_water = 0;
+
+               hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
+               lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
+
+               if (hi_water > 0xf)
+                       hi_water = 0xf;
+               else if (hi_water == 0)
+                       lo_water = 0;
+               val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
+       }
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
+}
+
 static int
 bnx2_set_mac_link(struct bnx2 *bp)
 {
@@ -1056,6 +1092,9 @@ bnx2_set_mac_link(struct bnx2 *bp)
        /* Acknowledge the interrupt. */
        REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               bnx2_init_rx_context0(bp);
+
        return 0;
 }
 
@@ -1390,7 +1429,7 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
 
        if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
-       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
+       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
 
        if (port == PORT_TP)
@@ -2237,7 +2276,7 @@ bnx2_init_context(struct bnx2 *bp)
 
                        /* Zero out the context. */
                        for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
-                               CTX_WR(bp, vcid_addr, offset, 0);
+                               bnx2_ctx_wr(bp, vcid_addr, offset, 0);
                }
        }
 }
@@ -4523,6 +4562,7 @@ static void
 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
 {
        u32 val, offset0, offset1, offset2, offset3;
+       u32 cid_addr = GET_CID_ADDR(cid);
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
                offset0 = BNX2_L2CTX_TYPE_XI;
@@ -4536,16 +4576,16 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
                offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
        }
        val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
+       bnx2_ctx_wr(bp, cid_addr, offset0, val);
 
        val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
-       CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
+       bnx2_ctx_wr(bp, cid_addr, offset1, val);
 
        val = (u64) bp->tx_desc_mapping >> 32;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
+       bnx2_ctx_wr(bp, cid_addr, offset2, val);
 
        val = (u64) bp->tx_desc_mapping & 0xffffffff;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
+       bnx2_ctx_wr(bp, cid_addr, offset3, val);
 }
 
 static void
@@ -4615,36 +4655,38 @@ bnx2_init_rx_ring(struct bnx2 *bp)
        bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
                             bp->rx_buf_use_size, bp->rx_max_ring);
 
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
+       bnx2_init_rx_context0(bp);
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
+               REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
+       }
+
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
        if (bp->rx_pg_ring_size) {
                bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
                                     bp->rx_pg_desc_mapping,
                                     PAGE_SIZE, bp->rx_max_pg_ring);
                val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
                       BNX2_L2CTX_RBDC_JUMBO_KEY);
 
                val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
 
                val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
 
                if (CHIP_NUM(bp) == CHIP_NUM_5709)
                        REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
        }
 
-       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
-       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
-       val |= 0x02 << 8;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
-
        val = (u64) bp->rx_desc_mapping[0] >> 32;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
 
        val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
 
        ring_prod = prod = bnapi->rx_pg_prod;
        for (i = 0; i < bp->rx_pg_ring_size; i++) {