#define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */
#define WKUP_LEN_P3_SHIFT 24
#define WKUP_LEN_D3 0x80000000
+#define WKUP_LEN_DISABLE 0x80808080
+#define WKUP_LEN_ENABLE_TWO 0x80800000
+#define WKUP_LEN_ENABLE_THREE 0x80000000
#define B44_ISTAT 0x0020UL /* Interrupt Status */
#define ISTAT_LS 0x00000020 /* Link Change (B0 only) */
#define ISTAT_PME 0x00000040 /* Power Management Event */
#define MII_TLEDCTRL_ENABLE 0x0040
struct dma_desc {
- u32 ctrl;
- u32 addr;
+ __le32 ctrl;
+ __le32 addr;
};
/* There are only 12 bits in the DMA engine for descriptor offsetting
#define RX_COPY_THRESHOLD 256
struct rx_header {
- u16 len;
- u16 flags;
- u16 pad[12];
+ __le16 len;
+ __le16 flags;
+ __le16 pad[12];
};
#define RX_HEADER_LEN 28