*
* ########################################################################
*
- *
+ *
*/
#define NUM_TX_BUFFS 4
#define MAX_BUF_SIZE 2048
-#define ETH_TX_TIMEOUT HZ/4
+#define ETH_TX_TIMEOUT (HZ/4)
#define MAC_MIN_PKT_SIZE 64
#define MULTICAST_FILTER_LIMIT 64
-/*
- * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
+/*
+ * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
* boundary for both, receive and transmit.
*/
typedef struct db_dest {
} db_dest_t;
/*
- * The transmit and receive descriptors are memory
+ * The transmit and receive descriptors are memory
* mapped registers.
*/
typedef struct tx_dma {
int old_duplex;
struct phy_device *phy_dev;
- struct mii_bus mii_bus;
-
+ struct mii_bus *mii_bus;
+
+ /* PHY configuration */
+ int phy_static_config;
+ int phy_search_highest_addr;
+ int phy1_search_mac0;
+
+ int phy_addr;
+ int phy_busid;
+ int phy_irq;
+
/* These variables are just for quick access to certain regs addresses. */
- volatile mac_reg_t *mac; /* mac registers */
+ volatile mac_reg_t *mac; /* mac registers */
volatile u32 *enable; /* address of MAC Enable Register */
u32 vaddr; /* virtual address of rx/tx buffers */
dma_addr_t dma_addr; /* dma address of rx/tx buffers */
- struct net_device_stats stats;
spinlock_t lock; /* Serialise access to device */
+
+ u32 msg_enable;
};