iobase_reg = inb(ioaddr+0x403);
membase_reg = inb(ioaddr+0x404);
/* ASIC location registers should be 0 or have only a single bit set. */
- if ( (iobase_reg & (iobase_reg - 1))
- || (membase_reg & (membase_reg - 1))) {
+ if ((iobase_reg & (iobase_reg - 1)) ||
+ (membase_reg & (membase_reg - 1))) {
retval = -ENODEV;
goto out1;
}
writel(0xba5eba5e, mem_base);
for (i = sizeof(test_val); i < EL2_MEMSIZE; i+=sizeof(test_val)) {
writel(test_val, mem_base + i);
- if (readl(mem_base) != 0xba5eba5e
- || readl(mem_base + i) != test_val) {
+ if (readl(mem_base) != 0xba5eba5e ||
+ readl(mem_base + i) != test_val) {
pr_warning("3c503: memory failure or memory address conflict.\n");
dev->mem_start = 0;
ei_status.name = "3c503-PIO";
static int
el2_open(struct net_device *dev)
{
- int retval = -EAGAIN;
+ int retval;
if (dev->irq < 2) {
int irqlist[] = {5, 9, 3, 4, 0};
outb(EGACFR_NORM, E33G_GACFR); /* Enable RAM and interrupts. */
do {
- if (request_irq (*irqp, NULL, 0, "bogus", dev) != -EBUSY) {
+ retval = request_irq(*irqp, NULL, 0, "bogus", dev);
+ if (retval >= 0) {
/* Twinkle the interrupt, and check if it's seen. */
unsigned long cookie = probe_irq_on();
outb_p(0x04 << ((*irqp == 9) ? 2 : *irqp), E33G_IDCFR);
outb_p(0x00, E33G_IDCFR);
- if (*irqp == probe_irq_off(cookie) /* It's a good IRQ line! */
- && ((retval = request_irq(dev->irq = *irqp,
- eip_interrupt, 0, dev->name, dev)) == 0))
+ if (*irqp == probe_irq_off(cookie) && /* It's a good IRQ line! */
+ ((retval = request_irq(dev->irq = *irqp,
+ eip_interrupt, 0,
+ dev->name, dev)) == 0))
break;
+ } else {
+ if (retval != -EBUSY)
+ return retval;
}
} while (*++irqp);
if (*irqp == 0) {
outb(EGACFR_IRQOFF, E33G_GACFR); /* disable interrupts. */
- return retval;
+ return -EAGAIN;
}
} else {
if ((retval = request_irq(dev->irq, eip_interrupt, 0, dev->name, dev))) {