eCryptfs: Remove mmap from directory operations

[safe/jmp/linux-2.6] / drivers / media / video / cx23885 / cx23885-reg.h

diff --git a/drivers/media/video/cx23885/cx23885-reg.h b/drivers/media/video/cx23885/cx23885-reg.h
index 5cb692f..c0bc9a0 100644 (file)
--- a/drivers/media/video/cx23885/cx23885-reg.h
+++ b/drivers/media/video/cx23885/cx23885-reg.h
@@ -1,7 +1,7 @@
 /*
  *  Driver for the Conexant CX23885 PCIe bridge
  *
- *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
+ *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -22,7 +22,6 @@
 #ifndef _CX23885_REG_H_
 #define _CX23885_REG_H_
 
-
 /*
 Address Map
 0x00000000 -> 0x00009000   TX SRAM  (Fifos)
@@ -50,8 +49,6 @@ Channel manager Data Structure entry = 20 DWORD
   5  InstructionQueueSize
 ...  Reserved
  19  Reserved
-
-
 */
 
 /* Risc Instructions */
@@ -70,22 +67,9 @@ Channel manager Data Structure entry = 20 DWORD
 #define RISC_WRITERM            0xB0000000
 #define RISC_WRITECM            0xC0000000
 #define RISC_WRITECR            0xD0000000
-
-//#define RISC_SYNC_ODD                 0x80000000
-//#define RISC_SYNC_EVEN                0x80000200
-//#define RISC_RESYNC_ODD               0x80008000
-//#define RISC_RESYNC_EVEN      0x80008200
-
-// Do we need these?
 #define RISC_WRITEC             0x50000000
 #define RISC_READC              0xA0000000
 
-// Is this used?
-#define RISC_IMM                0x00000001
-
-//#define RISC_CNT_NONE                 0x00000000
-//#define RISC_CNT_RSVR                 0x00020000
-//#define RISC_JMP_SRP                  0x01
 
 /* Audio and Video Core */
 #define HOST_REG1              0x00000000
@@ -227,7 +211,10 @@ Channel manager Data Structure entry = 20 DWORD
 #define I2S_TX_CFG     0x0000001A
 
 #define DEV_CNTRL2     0x00040000
-#define PCI_INT_MSK    0x00040010
+
+#define PCI_MSK_IR        (1 << 28)
+#define PCI_MSK_GPIO1     (1 << 24)
+#define PCI_MSK_GPIO0     (1 << 23)
 #define PCI_MSK_APB_DMA   (1 << 12)
 #define PCI_MSK_AL_WR     (1 << 11)
 #define PCI_MSK_AL_RD     (1 << 10)
@@ -238,6 +225,8 @@ Channel manager Data Structure entry = 20 DWORD
 #define PCI_MSK_VID_C     (1 <<  2)
 #define PCI_MSK_VID_B     (1 <<  1)
 #define PCI_MSK_VID_A      1
+#define PCI_INT_MSK    0x00040010
+
 #define PCI_INT_STAT   0x00040014
 #define PCI_INT_MSTAT  0x00040018
 
@@ -247,17 +236,44 @@ Channel manager Data Structure entry = 20 DWORD
 #define VID_A_INT_SSTAT        0x0004002C
 
 #define VID_B_INT_MSK  0x00040030
+#define VID_B_MSK_BAD_PKT     (1 << 20)
+#define VID_B_MSK_VBI_OPC_ERR (1 << 17)
+#define VID_B_MSK_OPC_ERR     (1 << 16)
+#define VID_B_MSK_VBI_SYNC    (1 << 13)
+#define VID_B_MSK_SYNC        (1 << 12)
+#define VID_B_MSK_VBI_OF      (1 <<  9)
+#define VID_B_MSK_OF          (1 <<  8)
+#define VID_B_MSK_VBI_RISCI2  (1 <<  5)
+#define VID_B_MSK_RISCI2      (1 <<  4)
+#define VID_B_MSK_VBI_RISCI1  (1 <<  1)
+#define VID_B_MSK_RISCI1       1
 #define VID_B_INT_STAT 0x00040034
 #define VID_B_INT_MSTAT        0x00040038
 #define VID_B_INT_SSTAT        0x0004003C
 
-#define VID_C_INT_MSK  0x00040040
+#define VID_B_MSK_BAD_PKT (1 << 20)
+#define VID_B_MSK_OPC_ERR (1 << 16)
+#define VID_B_MSK_SYNC    (1 << 12)
+#define VID_B_MSK_OF      (1 <<  8)
+#define VID_B_MSK_RISCI2  (1 <<  4)
+#define VID_B_MSK_RISCI1   1
+
 #define VID_C_MSK_BAD_PKT (1 << 20)
 #define VID_C_MSK_OPC_ERR (1 << 16)
 #define VID_C_MSK_SYNC    (1 << 12)
 #define VID_C_MSK_OF      (1 <<  8)
 #define VID_C_MSK_RISCI2  (1 <<  4)
 #define VID_C_MSK_RISCI1   1
+
+/* A superset for testing purposes */
+#define VID_BC_MSK_BAD_PKT (1 << 20)
+#define VID_BC_MSK_OPC_ERR (1 << 16)
+#define VID_BC_MSK_SYNC    (1 << 12)
+#define VID_BC_MSK_OF      (1 <<  8)
+#define VID_BC_MSK_RISCI2  (1 <<  4)
+#define VID_BC_MSK_RISCI1   1
+
+#define VID_C_INT_MSK  0x00040040
 #define VID_C_INT_STAT 0x00040044
 #define VID_C_INT_MSTAT        0x00040048
 #define VID_C_INT_SSTAT        0x0004004C
@@ -274,6 +290,7 @@ Channel manager Data Structure entry = 20 DWORD
 
 #define RDR_CFG0       0x00050000
 #define RDR_CFG1       0x00050004
+#define RDR_CFG2       0x00050008
 #define RDR_TLCTL0     0x00050318
 
 /* APB DMAC Current Buffer Pointer */
@@ -333,6 +350,7 @@ Channel manager Data Structure entry = 20 DWORD
 /* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
 #define MC417_OEN      0x00110024
 #define MC417_CTL      0x00110028
+#define ALT_PIN_OUT_SEL 0x0011002C
 #define CLK_DELAY      0x00110048
 #define PAD_CTRL       0x0011004C
 
@@ -351,8 +369,8 @@ Channel manager Data Structure entry = 20 DWORD
 #define VBI_B_DMA              0x00130108
 #define VID_B_GPCNT            0x00130120
 #define VBI_B_GPCNT            0x00130124
-#define VID_B_GPCNT_CTL                0x00130130
-#define VBI_B_GPCNT_CTL                0x00130134
+#define VID_B_GPCNT_CTL                0x00130134
+#define VBI_B_GPCNT_CTL                0x00130138
 #define VID_B_DMA_CTL          0x00130140
 #define VID_B_SRC_SEL          0x00130144
 #define VID_B_LNGTH            0x00130150