V4L/DVB (8914): cx18: Throttle mmio to/from the CX23418 so boards work in older systems

[safe/jmp/linux-2.6] / drivers / media / video / cx18 / cx18-driver.h

diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index 9c6a534..cc6f288 100644 (file)
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -38,7 +38,6 @@
 #include <linux/i2c-algo-bit.h>
 #include <linux/list.h>
 #include <linux/unistd.h>
-#include <linux/byteorder/swab.h>
 #include <linux/pagemap.h>
 #include <linux/workqueue.h>
 #include <linux/mutex.h>
@@ -46,6 +45,7 @@
 #include <linux/dvb/video.h>
 #include <linux/dvb/audio.h>
 #include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
 #include <media/tuner.h>
 #include "cx18-mailbox.h"
 #include "cx18-av-core.h"
@@ -63,6 +63,9 @@
 #  error "This driver requires kernel PCI support."
 #endif
 
+/* Default delay to throttle mmio access to the CX23418 so it doesn't choke */
+#define CX18_DEFAULT_MMIO_NDELAY 31 /* 30.3 ns = 1 PCI clock(s) / 33 MHz */
+
 #define CX18_MEM_OFFSET        0x00000000
 #define CX18_MEM_SIZE  0x04000000
 #define CX18_REG_OFFSET        0x02000000
@@ -75,7 +78,8 @@
 #define CX18_CARD_HVR_1600_SAMSUNG    1        /* Hauppauge HVR 1600 (Samsung memory) */
 #define CX18_CARD_COMPRO_H900        2 /* Compro VideoMate H900 */
 #define CX18_CARD_YUAN_MPC718        3 /* Yuan MPC718 */
-#define CX18_CARD_LAST                       3
+#define CX18_CARD_CNXT_RAPTOR_PAL     4        /* Conexant Raptor PAL */
+#define CX18_CARD_LAST                       4
 
 #define CX18_ENC_STREAM_TYPE_MPG  0
 #define CX18_ENC_STREAM_TYPE_TS   1
@@ -94,6 +98,7 @@
 #define CX18_PCI_ID_HAUPPAUGE          0x0070
 #define CX18_PCI_ID_COMPRO             0x185b
 #define CX18_PCI_ID_YUAN               0x12ab
+#define CX18_PCI_ID_CONEXANT           0x14f1
 
 /* ======================================================================== */
 /* ========================== START USER SETTABLE DMA VARIABLES =========== */
@@ -174,6 +179,7 @@ struct cx18_options {
        int cardtype;           /* force card type on load */
        int tuner;              /* set tuner on load */
        int radio;              /* enable/disable radio */
+       unsigned long mmio_ndelay; /* delay in ns after every PCI mmio access */
 };
 
 /* per-buffer bit flags */
@@ -213,8 +219,7 @@ struct cx18_buffer {
 
 struct cx18_queue {
        struct list_head list;
-       u32 buffers;
-       u32 length;
+       atomic_t buffers;
        u32 bytesused;
 };
 
@@ -228,14 +233,14 @@ struct cx18_dvb {
        struct dvb_net dvbnet;
        int enabled;
        int feeding;
-
        struct mutex feedlock;
-
 };
 
 struct cx18;    /* forward reference */
 struct cx18_scb; /* forward reference */
 
+#define CX18_INVALID_TASK_HANDLE 0xffffffff
+
 struct cx18_stream {
        /* These first four fields are always set, even if the stream
           is not actually created. */
@@ -258,7 +263,6 @@ struct cx18_stream {
        /* Buffer Stats */
        u32 buffers;
        u32 buf_size;
-       u32 buffers_stolen;
 
        /* Buffer Queues */
        struct cx18_queue q_free;       /* free buffers */
@@ -358,7 +362,7 @@ struct cx18 {
        u32 v4l2_cap;           /* V4L2 capabilities of card */
        u32 hw_flags;           /* Hardware description of the board */
        unsigned mdl_offset;
-       struct cx18_scb *scb;   /* pointer to SCB */
+       struct cx18_scb __iomem *scb;   /* pointer to SCB */
 
        struct cx18_av_state av_state;
 
@@ -424,6 +428,11 @@ struct cx18 {
        struct mutex i2c_bus_lock[2];
        struct i2c_client *i2c_clients[I2C_CLIENTS_MAX];
 
+       /* gpio */
+       u32 gpio_dir;
+       u32 gpio_val;
+       struct mutex gpio_lock;
+
        /* v4l2 and User settings */
 
        /* codec settings */
@@ -452,47 +461,4 @@ void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
 /* First-open initialization: load firmware, etc. */
 int cx18_init_on_first_open(struct cx18 *cx);
 
-/* This is a PCI post thing, where if the pci register is not read, then
-   the write doesn't always take effect right away. By reading back the
-   register any pending PCI writes will be performed (in order), and so
-   you can be sure that the writes are guaranteed to be done.
-
-   Rarely needed, only in some timing sensitive cases.
-   Apparently if this is not done some motherboards seem
-   to kill the firmware and get into the broken state until computer is
-   rebooted. */
-#define write_sync(val, reg) \
-       do { writel(val, reg); readl(reg); } while (0)
-
-#define read_reg(reg) readl(cx->reg_mem + (reg))
-#define write_reg(val, reg) writel(val, cx->reg_mem + (reg))
-#define write_reg_sync(val, reg) \
-       do { write_reg(val, reg); read_reg(reg); } while (0)
-
-#define read_enc(addr) readl(cx->enc_mem + (u32)(addr))
-#define write_enc(val, addr) writel(val, cx->enc_mem + (u32)(addr))
-#define write_enc_sync(val, addr) \
-       do { write_enc(val, addr); read_enc(addr); } while (0)
-
-#define sw1_irq_enable(val) do { \
-       write_reg(val, SW1_INT_STATUS); \
-       write_reg(read_reg(SW1_INT_ENABLE_PCI) | (val), SW1_INT_ENABLE_PCI); \
-} while (0)
-
-#define sw1_irq_disable(val) \
-       write_reg(read_reg(SW1_INT_ENABLE_PCI) & ~(val), SW1_INT_ENABLE_PCI);
-
-#define sw2_irq_enable(val) do { \
-       write_reg(val, SW2_INT_STATUS); \
-       write_reg(read_reg(SW2_INT_ENABLE_PCI) | (val), SW2_INT_ENABLE_PCI); \
-} while (0)
-
-#define sw2_irq_disable(val) \
-       write_reg(read_reg(SW2_INT_ENABLE_PCI) & ~(val), SW2_INT_ENABLE_PCI);
-
-#define setup_page(addr) do { \
-    u32 val = read_reg(0xD000F8) & ~0x1f00; \
-    write_reg(val | (((addr) >> 17) & 0x1f00), 0xD000F8); \
-} while (0)
-
 #endif /* CX18_DRIVER_H */