/*
* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
- * Copyright (C) 2003 Red Hat <alan@redhat.com>
+ * Copyright (C) 2003 Red Hat
* Copyright (C) 2007-2008 MontaVista Software, Inc.
* Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
*
* smarter code in libata.
*
* TODO:
- * - IORDY fixes
* - VDMA support
*/
static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
{
- ide_hwif_t *hwif = HWIF(drive);
+ ide_hwif_t *hwif = drive->hwif;
unsigned long base = (unsigned long)hwif->hwif_data;
u8 unit = drive->dn & 1;
* @pio: PIO mode number
*
* Load the timing settings for this device mode into the
- * controller. If we are in PIO mode 3 or 4 turn on IORDY
- * monitoring (bit 9). The TF timing is bits 31:16
+ * controller.
*/
static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
- ide_hwif_t *hwif = HWIF(drive);
+ ide_hwif_t *hwif = drive->hwif;
struct pci_dev *dev = to_pci_dev(hwif->dev);
ide_drive_t *pair = ide_get_pair_dev(drive);
u32 speedt = 0;
/* now set up IORDY */
speedp = sil_ioread16(dev, tfaddr - 2);
speedp &= ~0x200;
- if (pio > 2)
- speedp |= 0x200;
- sil_iowrite16(dev, speedp, tfaddr - 2);
mode = sil_ioread8(dev, base + addr_mask);
mode &= ~(unit ? 0x30 : 0x03);
- mode |= unit ? 0x10 : 0x01;
+
+ if (ide_pio_need_iordy(drive, pio)) {
+ speedp |= 0x200;
+ mode |= unit ? 0x10 : 0x01;
+ }
+
+ sil_iowrite16(dev, speedp, tfaddr - 2);
sil_iowrite8(dev, mode, base + addr_mask);
}
static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
- ide_hwif_t *hwif = HWIF(drive);
+ ide_hwif_t *hwif = drive->hwif;
struct pci_dev *dev = to_pci_dev(hwif->dev);
unsigned long base = (unsigned long)hwif->hwif_data;
u16 ultra = 0, multi = 0;
sil_iowrite16(dev, ultra, ua);
}
-/* returns 1 if dma irq issued, 0 otherwise */
-static int siimage_io_dma_test_irq(ide_drive_t *drive)
+static int sil_test_irq(ide_hwif_t *hwif)
{
- ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = to_pci_dev(hwif->dev);
- u8 dma_altstat = 0;
unsigned long addr = siimage_selreg(hwif, 1);
+ u8 val = sil_ioread8(dev, addr);
- /* return 1 if INTR asserted */
- if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4)
- return 1;
-
- /* return 1 if Device INTR asserted */
- pci_read_config_byte(dev, addr, &dma_altstat);
- if (dma_altstat & 8)
- return 0; /* return 1; */
-
- return 0;
+ /* Return 1 if INTRQ asserted */
+ return (val & 8) ? 1 : 0;
}
/**
static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
{
- ide_hwif_t *hwif = HWIF(drive);
- unsigned long addr = siimage_selreg(hwif, 0x1);
+ ide_hwif_t *hwif = drive->hwif;
void __iomem *sata_error_addr
= (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
return 1;
- /* return 1 if Device INTR asserted */
- if (readb((void __iomem *)addr) & 8)
- return 0; /* return 1; */
-
return 0;
}
if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
return siimage_mmio_dma_test_irq(drive);
else
- return siimage_io_dma_test_irq(drive);
+ return ide_dma_test_irq(drive);
}
/**
static void sil_sata_pre_reset(ide_drive_t *drive)
{
if (drive->media == ide_disk) {
- drive->special.b.set_geometry = 0;
- drive->special.b.recalibrate = 0;
+ drive->special_flags &=
+ ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
}
}
* to 133 MHz clocking if the system isn't already set up to do it.
*/
-static unsigned int init_chipset_siimage(struct pci_dev *dev)
+static int init_chipset_siimage(struct pci_dev *dev)
{
struct ide_host *host = pci_get_drvdata(dev);
void __iomem *ioaddr = host->host_priv;
.set_pio_mode = sil_set_pio_mode,
.set_dma_mode = sil_set_dma_mode,
.quirkproc = sil_quirkproc,
+ .test_irq = sil_test_irq,
.udma_filter = sil_pata_udma_filter,
.cable_detect = sil_cable_detect,
};
.reset_poll = sil_sata_reset_poll,
.pre_reset = sil_sata_pre_reset,
.quirkproc = sil_quirkproc,
+ .test_irq = sil_test_irq,
.udma_filter = sil_sata_udma_filter,
.cable_detect = sil_cable_detect,
};
static const struct ide_dma_ops sil_dma_ops = {
.dma_host_set = ide_dma_host_set,
.dma_setup = ide_dma_setup,
- .dma_exec_cmd = ide_dma_exec_cmd,
.dma_start = ide_dma_start,
.dma_end = ide_dma_end,
.dma_test_irq = siimage_dma_test_irq,
- .dma_timeout = ide_dma_timeout,
+ .dma_timer_expiry = ide_dma_sff_timer_expiry,
.dma_lost_irq = ide_dma_lost_irq,
+ .dma_sff_read_status = ide_dma_sff_read_status,
};
#define DECLARE_SII_DEV(p_ops) \
printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
"available\n", pci_name(dev));
} else {
- ioaddr = ioremap(bar5, barsize);
+ ioaddr = pci_ioremap_bar(dev, 5);
if (ioaddr == NULL)
release_mem_region(bar5, barsize);
}