#define DRVNAME "coretemp"
-typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_LABEL, SHOW_NAME } SHOW;
+typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
+ SHOW_NAME } SHOW;
/*
* Functions declaration
unsigned long last_updated; /* in jiffies */
int temp;
int tjmax;
+ int ttarget;
u8 alarm;
};
if (attr->index == SHOW_TEMP)
err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
- else
+ else if (attr->index == SHOW_TJMAX)
err = sprintf(buf, "%d\n", data->tjmax);
-
+ else
+ err = sprintf(buf, "%d\n", data->ttarget);
return err;
}
SHOW_TEMP);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
SHOW_TJMAX);
+static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
+ SHOW_TTARGET);
static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
return data;
}
+static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+ /* The 100C is default for both mobile and non mobile CPUs */
+
+ int tjmax = 100000;
+ int tjmax_ee = 85000;
+ int usemsr_ee = 1;
+ int err;
+ u32 eax, edx;
+
+ /* Early chips have no MSR for TjMax */
+
+ if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
+ usemsr_ee = 0;
+ }
+
+ /* Atoms seems to have TjMax at 90C */
+
+ if (c->x86_model == 0x1c) {
+ usemsr_ee = 0;
+ tjmax = 90000;
+ }
+
+ if ((c->x86_model > 0xe) && (usemsr_ee)) {
+ u8 platform_id;
+
+ /* Now we can detect the mobile CPU using Intel provided table
+ http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
+ For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
+ */
+
+ err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
+ if (err) {
+ dev_warn(dev,
+ "Unable to access MSR 0x17, assuming desktop"
+ " CPU\n");
+ usemsr_ee = 0;
+ } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
+ /* Trust bit 28 up to Penryn, I could not find any
+ documentation on that; if you happen to know
+ someone at Intel please ask */
+ usemsr_ee = 0;
+ } else {
+ /* Platform ID bits 52:50 (EDX starts at bit 32) */
+ platform_id = (edx >> 18) & 0x7;
+
+ /* Mobile Penryn CPU seems to be platform ID 7 or 5
+ (guesswork) */
+ if ((c->x86_model == 0x17) &&
+ ((platform_id == 5) || (platform_id == 7))) {
+ /* If MSR EE bit is set, set it to 90 degrees C,
+ otherwise 105 degrees C */
+ tjmax_ee = 90000;
+ tjmax = 105000;
+ }
+ }
+ }
+
+ if (usemsr_ee) {
+
+ err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
+ if (err) {
+ dev_warn(dev,
+ "Unable to access MSR 0xEE, for Tjmax, left"
+ " at default");
+ } else if (eax & 0x40000000) {
+ tjmax = tjmax_ee;
+ }
+ /* if we dont use msr EE it means we are desktop CPU (with exeception
+ of Atom) */
+ } else if (tjmax == 100000) {
+ dev_warn(dev, "Using relative temperature scale!\n");
+ }
+
+ return tjmax;
+}
+
static int __devinit coretemp_probe(struct platform_device *pdev)
{
struct coretemp_data *data;
data->id = pdev->id;
data->name = "coretemp";
mutex_init(&data->update_lock);
- /* Tjmax default is 100 degrees C */
- data->tjmax = 100000;
/* test if we can access the THERM_STATUS MSR */
err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
}
}
- /* Some processors have Tjmax 85 following magic should detect it
- Intel won't disclose the information without signed NDA, but
- individuals cannot sign it. Catch(ed) 22.
- */
+ data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+ platform_set_drvdata(pdev, data);
+
+ /* read the still undocumented IA32_TEMPERATURE_TARGET it exists
+ on older CPUs but not in this register, Atoms don't have it either */
- if (((c->x86_model == 0xf) && (c->x86_mask > 3)) ||
- (c->x86_model == 0xe)) {
- err = rdmsr_safe_on_cpu(data->id, 0xee, &eax, &edx);
+ if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
+ err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
if (err) {
- dev_warn(&pdev->dev,
- "Unable to access MSR 0xEE, Tjmax left at %d "
- "degrees C\n", data->tjmax/1000);
- } else if (eax & 0x40000000) {
- data->tjmax = 85000;
+ dev_warn(&pdev->dev, "Unable to read"
+ " IA32_TEMPERATURE_TARGET MSR\n");
+ } else {
+ data->ttarget = data->tjmax -
+ (((eax >> 8) & 0xff) * 1000);
+ err = device_create_file(&pdev->dev,
+ &sensor_dev_attr_temp1_max.dev_attr);
+ if (err)
+ goto exit_free;
}
}
- /* Intel says that above should not work for desktop Core2 processors,
- but it seems to work. There is no other way how get the absolute
- readings. Warn the user about this. First check if are desktop,
- bit 50 of MSR_IA32_PLATFORM_ID should be 0.
- */
-
- rdmsr_safe_on_cpu(data->id, MSR_IA32_PLATFORM_ID, &eax, &edx);
-
- if ((c->x86_model == 0xf) && (!(edx & 0x00040000))) {
- dev_warn(&pdev->dev, "Using undocumented features, absolute "
- "temperature might be wrong!\n");
- }
-
- platform_set_drvdata(pdev, data);
-
if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
- goto exit_free;
+ goto exit_dev;
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
exit_class:
sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
+exit_dev:
+ device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
exit_free:
kfree(data);
exit:
hwmon_device_unregister(data->hwmon_dev);
sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
+ device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
platform_set_drvdata(pdev, NULL);
kfree(data);
return 0;
mutex_unlock(&pdev_list_mutex);
}
-static int coretemp_cpu_callback(struct notifier_block *nfb,
+static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long) hcpu;
switch (action) {
case CPU_ONLINE:
- case CPU_ONLINE_FROZEN:
+ case CPU_DOWN_FAILED:
coretemp_device_add(cpu);
break;
- case CPU_DEAD:
- case CPU_DEAD_FROZEN:
+ case CPU_DOWN_PREPARE:
coretemp_device_remove(cpu);
break;
}
return NOTIFY_OK;
}
-static struct notifier_block coretemp_cpu_notifier = {
+static struct notifier_block coretemp_cpu_notifier __refdata = {
.notifier_call = coretemp_cpu_callback,
};
#endif /* !CONFIG_HOTPLUG_CPU */
for_each_online_cpu(i) {
struct cpuinfo_x86 *c = &cpu_data(i);
- /* check if family 6, models e, f, 16 */
+ /* check if family 6, models 0xe (Pentium M DC),
+ 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
+ 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
+ 0x1e (Lynnfield) */
if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
!((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
- (c->x86_model == 0x16))) {
+ (c->x86_model == 0x16) || (c->x86_model == 0x17) ||
+ (c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
+ (c->x86_model == 0x1e))) {
/* supported CPU not found, but report the unknown
family 6 CPU */
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff