radeon: Fix CP byte order on big endian architectures with KMS.

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / radeon_reg.h

diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 6d3d904..e1b6185 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3184,6 +3184,7 @@
 #      define RADEON_RB_BUFSZ_MASK             (0x3f << 0)
 #      define RADEON_RB_BLKSZ_SHIFT            8
 #      define RADEON_RB_BLKSZ_MASK             (0x3f << 8)
+#      define RADEON_BUF_SWAP_32BIT            (1 << 17)
 #      define RADEON_MAX_FETCH_SHIFT           18
 #      define RADEON_MAX_FETCH_MASK            (0x3 << 18)
 #      define RADEON_RB_NO_UPDATE              (1 << 27)