drm/radeon: include radeon_asic.h in the asic specific files

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / r600.c

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 694a4c5..5b00d5e 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -31,6 +31,7 @@
 #include "drmP.h"
 #include "radeon_drm.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "radeon_mode.h"
 #include "r600d.h"
 #include "atom.h"
@@ -712,6 +713,7 @@ int r600_mc_init(struct radeon_device *rdev)
        /* Setup GPU memory space */
        rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
        rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
+       rdev->mc.visible_vram_size = rdev->mc.aper_size;
        /* FIXME remove this once we support unmappable VRAM */
        if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
                rdev->mc.mc_vram_size = rdev->mc.aper_size;
@@ -980,6 +982,9 @@ void r600_gpu_init(struct radeon_device *rdev)
 {
        u32 tiling_config;
        u32 ramcfg;
+       u32 backend_map;
+       u32 cc_rb_backend_disable;
+       u32 cc_gc_shader_pipe_config;
        u32 tmp;
        int i, j;
        u32 sq_config;
@@ -1076,23 +1081,20 @@ void r600_gpu_init(struct radeon_device *rdev)
        switch (rdev->config.r600.max_tile_pipes) {
        case 1:
                tiling_config |= PIPE_TILING(0);
-               rdev->config.r600.tiling_npipes = 1;
                break;
        case 2:
                tiling_config |= PIPE_TILING(1);
-               rdev->config.r600.tiling_npipes = 2;
                break;
        case 4:
                tiling_config |= PIPE_TILING(2);
-               rdev->config.r600.tiling_npipes = 4;
                break;
        case 8:
                tiling_config |= PIPE_TILING(3);
-               rdev->config.r600.tiling_npipes = 8;
                break;
        default:
                break;
        }
+       rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
        rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
        tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
        tiling_config |= GROUP_SIZE(0);
@@ -1106,24 +1108,33 @@ void r600_gpu_init(struct radeon_device *rdev)
                tiling_config |= SAMPLE_SPLIT(tmp);
        }
        tiling_config |= BANK_SWAPS(1);
-       tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
-                                               rdev->config.r600.max_backends,
-                                               (0xff << rdev->config.r600.max_backends) & 0xff);
-       tiling_config |= BACKEND_MAP(tmp);
+
+       cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
+       cc_rb_backend_disable |=
+               BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
+
+       cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
+       cc_gc_shader_pipe_config |=
+               INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
+       cc_gc_shader_pipe_config |=
+               INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
+
+       backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
+                                                       (R6XX_MAX_BACKENDS -
+                                                        r600_count_pipe_bits((cc_rb_backend_disable &
+                                                                              R6XX_MAX_BACKENDS_MASK) >> 16)),
+                                                       (cc_rb_backend_disable >> 16));
+
+       tiling_config |= BACKEND_MAP(backend_map);
        WREG32(GB_TILING_CONFIG, tiling_config);
        WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
        WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 
-       tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
-       WREG32(CC_RB_BACKEND_DISABLE, tmp);
-
        /* Setup pipes */
-       tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
-       tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
-       WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
-       WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
+       WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+       WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 
-       tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
+       tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
        WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
        WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 
@@ -1960,6 +1971,13 @@ int r600_resume(struct radeon_device *rdev)
                DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                return r;
        }
+
+       r = r600_audio_init(rdev);
+       if (r) {
+               DRM_ERROR("radeon: audio resume failed\n");
+               return r;
+       }
+
        return r;
 }
 
@@ -1967,6 +1985,7 @@ int r600_suspend(struct radeon_device *rdev)
 {
        int r;
 
+       r600_audio_fini(rdev);
        /* FIXME: we should wait for ring to be empty */
        r600_cp_stop(rdev);
        rdev->cp.ready = false;
@@ -2747,6 +2766,7 @@ restart_ih:
                        case 0: /* D1 vblank */
                                if (disp_int & LB_D1_VBLANK_INTERRUPT) {
                                        drm_handle_vblank(rdev->ddev, 0);
+                                       rdev->pm.vblank_sync = true;
                                        wake_up(&rdev->irq.vblank_queue);
                                        disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
@@ -2768,6 +2788,7 @@ restart_ih:
                        case 0: /* D2 vblank */
                                if (disp_int & LB_D2_VBLANK_INTERRUPT) {
                                        drm_handle_vblank(rdev->ddev, 1);
+                                       rdev->pm.vblank_sync = true;
                                        wake_up(&rdev->irq.vblank_queue);
                                        disp_int &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");