radeon: Fix CP byte order on big endian architectures with KMS.

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / r100.c

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 8f41f70..64a692c 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -551,6 +551,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        /* cp setup */
        WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
        WREG32(RADEON_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+              RADEON_BUF_SWAP_32BIT |
+#endif
               REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
               REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
               REG_SET(RADEON_MAX_FETCH, max_fetch) |