Merge branch 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspe...

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / atombios_crtc.c

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a8cd637..fd4ef6d 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -521,12 +521,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
                                        adjusted_clock = mode->clock * 2;
-                               /* LVDS PLL quirks */
-                               if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
-                                       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-                                       pll->algo = dig->pll_algo;
-                                       pll->flags |= RADEON_PLL_IS_LCD;
-                               }
                        } else {
                                if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
                                        pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -547,8 +541,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                int index;
 
                index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
-               atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                                     &crev);
+               if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                          &crev))
+                       return adjusted_clock;
 
                memset(&args, 0, sizeof(args));
 
@@ -586,11 +581,16 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                        }
                                } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
                                        /* may want to enable SS on DP/eDP eventually */
-                                       args.v3.sInput.ucDispPllConfig |=
-                                               DISPPLL_CONFIG_SS_ENABLE;
-                                       if (mode->clock > 165000)
+                                       /*args.v3.sInput.ucDispPllConfig |=
+                                               DISPPLL_CONFIG_SS_ENABLE;*/
+                                       if (encoder_mode == ATOM_ENCODER_MODE_DP)
                                                args.v3.sInput.ucDispPllConfig |=
-                                                       DISPPLL_CONFIG_DUAL_LINK;
+                                                       DISPPLL_CONFIG_COHERENT_MODE;
+                                       else {
+                                               if (mode->clock > 165000)
+                                                       args.v3.sInput.ucDispPllConfig |=
+                                                               DISPPLL_CONFIG_DUAL_LINK;
+                                       }
                                }
                                atom_execute_table(rdev->mode_info.atom_context,
                                                   index, (uint32_t *)&args);
@@ -636,8 +636,9 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
        memset(&args, 0, sizeof(args));
 
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-       atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                             &crev);
+       if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                  &crev))
+               return;
 
        switch (frev) {
        case 1:
@@ -711,8 +712,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                           &ref_div, &post_div);
 
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-       atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                             &crev);
+       if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                  &crev))
+               return;
 
        switch (frev) {
        case 1:
@@ -1127,9 +1129,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
 
        /* TODO color tiling */
 
-       /* pick pll */
-       radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
-
        atombios_disable_ss(crtc);
        /* always set DCPLL */
        if (ASIC_IS_DCE4(rdev))
@@ -1164,6 +1163,11 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 
 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 {
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+       /* pick pll */
+       radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
+
        atombios_lock_crtc(crtc, ATOM_ENABLE);
        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }