Merge branch 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspe...
[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / atombios_crtc.c
index 7e7c0b3..fd4ef6d 100644 (file)
@@ -245,10 +245,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 
        switch (mode) {
        case DRM_MODE_DPMS_ON:
-               atombios_enable_crtc(crtc, 1);
+               atombios_enable_crtc(crtc, ATOM_ENABLE);
                if (ASIC_IS_DCE3(rdev))
-                       atombios_enable_crtc_memreq(crtc, 1);
-               atombios_blank_crtc(crtc, 0);
+                       atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
+               atombios_blank_crtc(crtc, ATOM_DISABLE);
                /* XXX re-enable when interrupt support is added */
                if (!ASIC_IS_DCE4(rdev))
                        drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
@@ -260,10 +260,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
                /* XXX re-enable when interrupt support is added */
                if (!ASIC_IS_DCE4(rdev))
                        drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
-               atombios_blank_crtc(crtc, 1);
+               atombios_blank_crtc(crtc, ATOM_ENABLE);
                if (ASIC_IS_DCE3(rdev))
-                       atombios_enable_crtc_memreq(crtc, 0);
-               atombios_enable_crtc(crtc, 0);
+                       atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
+               atombios_enable_crtc(crtc, ATOM_DISABLE);
                break;
        }
 }
@@ -353,12 +353,55 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
+static void atombios_disable_ss(struct drm_crtc *crtc)
+{
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+       u32 ss_cntl;
+
+       if (ASIC_IS_DCE4(rdev)) {
+               switch (radeon_crtc->pll_id) {
+               case ATOM_PPLL1:
+                       ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
+                       ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
+                       WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
+                       break;
+               case ATOM_PPLL2:
+                       ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
+                       ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
+                       WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
+                       break;
+               case ATOM_DCPLL:
+               case ATOM_PPLL_INVALID:
+                       return;
+               }
+       } else if (ASIC_IS_AVIVO(rdev)) {
+               switch (radeon_crtc->pll_id) {
+               case ATOM_PPLL1:
+                       ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
+                       ss_cntl &= ~1;
+                       WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
+                       break;
+               case ATOM_PPLL2:
+                       ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
+                       ss_cntl &= ~1;
+                       WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
+                       break;
+               case ATOM_DCPLL:
+               case ATOM_PPLL_INVALID:
+                       return;
+               }
+       }
+}
+
+
 union atom_enable_ss {
        ENABLE_LVDS_SS_PARAMETERS legacy;
        ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 };
 
-static void atombios_set_ss(struct drm_crtc *crtc, int enable)
+static void atombios_enable_ss(struct drm_crtc *crtc)
 {
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
@@ -387,9 +430,9 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
                                        step = dig->ss->step;
                                        delay = dig->ss->delay;
                                        range = dig->ss->range;
-                               } else if (enable)
+                               } else
                                        return;
-                       } else if (enable)
+                       } else
                                return;
                        break;
                }
@@ -406,13 +449,13 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
                args.v1.ucSpreadSpectrumDelay = delay;
                args.v1.ucSpreadSpectrumRange = range;
                args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-               args.v1.ucEnable = enable;
+               args.v1.ucEnable = ATOM_ENABLE;
        } else {
                args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
                args.legacy.ucSpreadSpectrumType = type;
                args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
                args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
-               args.legacy.ucEnable = enable;
+               args.legacy.ucEnable = ATOM_ENABLE;
        }
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
@@ -438,12 +481,16 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 
        /* select the PLL algo */
        if (ASIC_IS_AVIVO(rdev)) {
-               if (radeon_new_pll)
-                       pll->algo = PLL_ALGO_AVIVO;
+               if (radeon_new_pll == 0)
+                       pll->algo = PLL_ALGO_LEGACY;
+               else
+                       pll->algo = PLL_ALGO_NEW;
+       } else {
+               if (radeon_new_pll == 1)
+                       pll->algo = PLL_ALGO_NEW;
                else
                        pll->algo = PLL_ALGO_LEGACY;
-       } else
-               pll->algo = PLL_ALGO_LEGACY;
+       }
 
        if (ASIC_IS_AVIVO(rdev)) {
                if ((rdev->family == CHIP_RS600) ||
@@ -474,11 +521,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
                                        adjusted_clock = mode->clock * 2;
-                               /* LVDS PLL quirks */
-                               if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
-                                       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-                                       pll->algo = dig->pll_algo;
-                               }
                        } else {
                                if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
                                        pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -499,8 +541,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                int index;
 
                index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
-               atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                                     &crev);
+               if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                          &crev))
+                       return adjusted_clock;
 
                memset(&args, 0, sizeof(args));
 
@@ -538,11 +581,16 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                        }
                                } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
                                        /* may want to enable SS on DP/eDP eventually */
-                                       args.v3.sInput.ucDispPllConfig |=
-                                               DISPPLL_CONFIG_SS_ENABLE;
-                                       if (mode->clock > 165000)
+                                       /*args.v3.sInput.ucDispPllConfig |=
+                                               DISPPLL_CONFIG_SS_ENABLE;*/
+                                       if (encoder_mode == ATOM_ENCODER_MODE_DP)
                                                args.v3.sInput.ucDispPllConfig |=
-                                                       DISPPLL_CONFIG_DUAL_LINK;
+                                                       DISPPLL_CONFIG_COHERENT_MODE;
+                                       else {
+                                               if (mode->clock > 165000)
+                                                       args.v3.sInput.ucDispPllConfig |=
+                                                               DISPPLL_CONFIG_DUAL_LINK;
+                                       }
                                }
                                atom_execute_table(rdev->mode_info.atom_context,
                                                   index, (uint32_t *)&args);
@@ -588,8 +636,9 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
        memset(&args, 0, sizeof(args));
 
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-       atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                             &crev);
+       if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                  &crev))
+               return;
 
        switch (frev) {
        case 1:
@@ -663,8 +712,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                           &ref_div, &post_div);
 
        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
-       atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
-                             &crev);
+       if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                  &crev))
+               return;
 
        switch (frev) {
        case 1:
@@ -1079,15 +1129,12 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
 
        /* TODO color tiling */
 
-       /* pick pll */
-       radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
-
-       atombios_set_ss(crtc, 0);
+       atombios_disable_ss(crtc);
        /* always set DCPLL */
        if (ASIC_IS_DCE4(rdev))
                atombios_crtc_set_dcpll(crtc);
        atombios_crtc_set_pll(crtc, adjusted_mode);
-       atombios_set_ss(crtc, 1);
+       atombios_enable_ss(crtc);
 
        if (ASIC_IS_DCE4(rdev))
                atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
@@ -1116,14 +1163,19 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 
 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 {
-       atombios_lock_crtc(crtc, 1);
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+       /* pick pll */
+       radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
+
+       atombios_lock_crtc(crtc, ATOM_ENABLE);
        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }
 
 static void atombios_crtc_commit(struct drm_crtc *crtc)
 {
        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
-       atombios_lock_crtc(crtc, 0);
+       atombios_lock_crtc(crtc, ATOM_DISABLE);
 }
 
 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
@@ -1145,22 +1197,22 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
                switch (radeon_crtc->crtc_id) {
                case 0:
                default:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
                        break;
                case 1:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
                        break;
                case 2:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
                        break;
                case 3:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
                        break;
                case 4:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
                        break;
                case 5:
-                       radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET;
+                       radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
                        break;
                }
        } else {