drm/radeon/kms/atom: add support for AdjustDisplayPll

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / atombios_crtc.c

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a7edd0f..d5e6f3d 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -248,18 +248,18 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 
        switch (mode) {
        case DRM_MODE_DPMS_ON:
+               atombios_enable_crtc(crtc, 1);
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 1);
-               atombios_enable_crtc(crtc, 1);
                atombios_blank_crtc(crtc, 0);
                break;
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
        case DRM_MODE_DPMS_OFF:
                atombios_blank_crtc(crtc, 1);
-               atombios_enable_crtc(crtc, 0);
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 0);
+               atombios_enable_crtc(crtc, 0);
                break;
        }
 
@@ -333,12 +333,13 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        struct drm_encoder *encoder = NULL;
        struct radeon_encoder *radeon_encoder = NULL;
        uint8_t frev, crev;
-       int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+       int index;
        SET_PIXEL_CLOCK_PS_ALLOCATION args;
        PIXEL_CLOCK_PARAMETERS *spc1_ptr;
        PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
        PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
-       uint32_t sclock = mode->clock;
+       uint32_t pll_clock = mode->clock;
+       uint32_t adjusted_clock;
        uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
        struct radeon_pll *pll;
        int pll_flags = 0;
@@ -393,12 +394,34 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                }
        }
 
+       /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
+        * accordingly based on the encoder/transmitter to work around
+        * special hw requirements.
+        */
+       if (ASIC_IS_DCE3(rdev)) {
+               ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
+
+               if (!encoder)
+                       return;
+
+               memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
+               adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
+               adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
+               adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
+
+               index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+               atom_execute_table(rdev->mode_info.atom_context,
+                                  index, (uint32_t *)&adjust_pll_args);
+               adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
+       } else
+               adjusted_clock = mode->clock;
+
        if (radeon_crtc->crtc_id == 0)
                pll = &rdev->clock.p1pll;
        else
                pll = &rdev->clock.p2pll;
 
-       radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
+       radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
                           &ref_div, &post_div, pll_flags);
 
        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
@@ -409,7 +432,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                switch (crev) {
                case 1:
                        spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
-                       spc1_ptr->usPixelClock = cpu_to_le16(sclock);
+                       spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc1_ptr->ucFracFbDiv = frac_fb_div;
@@ -422,7 +445,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                case 2:
                        spc2_ptr =
                            (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
-                       spc2_ptr->usPixelClock = cpu_to_le16(sclock);
+                       spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc2_ptr->ucFracFbDiv = frac_fb_div;
@@ -437,7 +460,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                                return;
                        spc3_ptr =
                            (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
-                       spc3_ptr->usPixelClock = cpu_to_le16(sclock);
+                       spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc3_ptr->ucFracFbDiv = frac_fb_div;
@@ -460,6 +483,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        }
 
        printk("executing set pll\n");
+       index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
@@ -488,6 +512,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
        }
 
        switch (crtc->fb->bits_per_pixel) {
+       case 8:
+               fb_format =
+                   AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
+                   AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
+               break;
        case 15:
                fb_format =
                    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
@@ -558,6 +587,10 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                radeon_fb = to_radeon_framebuffer(old_fb);
                radeon_gem_object_unpin(radeon_fb->obj);
        }
+
+       /* Bytes per pixel may have changed */
+       radeon_bandwidth_update(rdev);
+
        return 0;
 }
 
@@ -696,7 +729,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
        }
        atombios_overscan_setup(crtc, mode, adjusted_mode);
        atombios_scaler_setup(crtc);
-       radeon_bandwidth_update(rdev);
        return 0;
 }
 
@@ -728,6 +760,7 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
        .mode_set_base = atombios_crtc_set_base,
        .prepare = atombios_crtc_prepare,
        .commit = atombios_crtc_commit,
+       .load_lut = radeon_crtc_load_lut,
 };
 
 void radeon_atombios_init_crtc(struct drm_device *dev,