Merge commit 'v2.6.32-rc7'

[safe/jmp/linux-2.6] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f92724..1687edf 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1080,6 +1080,8 @@
 #define   BACKLIGHT_DUTY_CYCLE_SHIFT           (0)
 #define   BACKLIGHT_DUTY_CYCLE_MASK            (0xffff)
 
+#define BLC_HIST_CTL           0x61260
+
 /* TV port control */
 #define TV_CTL                 0x68000
 /** Enables the TV encoder */
@@ -1782,6 +1784,11 @@
 #define   PIPE_START_VBLANK_INTERRUPT_STATUS   (1UL<<2) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_STATUS         (1UL<<1)
 #define   PIPE_OVERLAY_UPDATED_STATUS          (1UL<<0)
+#define   PIPE_BPC_MASK                        (7 << 5) /* Ironlake */
+#define   PIPE_8BPC                            (0 << 5)
+#define   PIPE_10BPC                           (1 << 5)
+#define   PIPE_6BPC                            (2 << 5)
+#define   PIPE_12BPC                           (3 << 5)
 
 #define DSPARB                 0x70030
 #define   DSPARB_CSTART_MASK   (0x7f << 7)
@@ -1792,17 +1799,29 @@
 #define   DSPARB_AEND_SHIFT    0
 
 #define DSPFW1                 0x70034
+#define   DSPFW_SR_SHIFT       23
+#define   DSPFW_CURSORB_SHIFT  16
+#define   DSPFW_PLANEB_SHIFT   8
 #define DSPFW2                 0x70038
+#define   DSPFW_CURSORA_MASK   0x00003f00
+#define   DSPFW_CURSORA_SHIFT  16
 #define DSPFW3                 0x7003c
+#define   DSPFW_HPLL_SR_EN     (1<<31)
+#define   DSPFW_CURSOR_SR_SHIFT        24
 #define   IGD_SELF_REFRESH_EN  (1<<30)
 
 /* FIFO watermark sizes etc */
+#define G4X_FIFO_LINE_SIZE     64
 #define I915_FIFO_LINE_SIZE    64
 #define I830_FIFO_LINE_SIZE    32
+
+#define G4X_FIFO_SIZE          127
 #define I945_FIFO_SIZE         127 /* 945 & 965 */
 #define I915_FIFO_SIZE         95
 #define I855GM_FIFO_SIZE       127 /* In cachelines */
 #define I830_FIFO_SIZE         95
+
+#define G4X_MAX_WM             0x3f
 #define I915_MAX_WM            0x3f
 
 #define IGD_DISPLAY_FIFO       512 /* in 64byte unit */
@@ -2032,6 +2051,11 @@
 #define PFA_CTL_1               0x68080
 #define PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_FILTER_MASK                (3<<23)
+#define  PF_FILTER_PROGRAMMED  (0<<23)
+#define  PF_FILTER_MED_3x3     (1<<23)
+#define  PF_FILTER_EDGE_ENHANCE        (2<<23)
+#define  PF_FILTER_EDGE_SOFTEN (3<<23)
 #define PFA_WIN_SZ             0x68074
 #define PFB_WIN_SZ             0x68874
 #define PFA_WIN_POS            0x68070
@@ -2151,11 +2175,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK           (3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK                  (2<<11)
+#define  DREF_SSC_SOURCE_MASK                  (3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE           (1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK            (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK            (3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)