Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt...

[safe/jmp/linux-2.6] / drivers / gpu / drm / i915 / i915_gem.c

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4408da..670d128 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1145,6 +1145,13 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
                        mutex_unlock(&dev->struct_mutex);
                        return VM_FAULT_SIGBUS;
                }
+
+               ret = i915_gem_object_set_to_gtt_domain(obj, write);
+               if (ret) {
+                       mutex_unlock(&dev->struct_mutex);
+                       return VM_FAULT_SIGBUS;
+               }
+
                list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
        }
 
@@ -2423,6 +2430,16 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
        if (obj_priv->pages == NULL)
                return;
 
+       /* XXX: The 865 in particular appears to be weird in how it handles
+        * cache flushing.  We haven't figured it out, but the
+        * clflush+agp_chipset_flush doesn't appear to successfully get the
+        * data visible to the PGU, while wbinvd + agp_chipset_flush does.
+        */
+       if (IS_I865G(obj->dev)) {
+               wbinvd();
+               return;
+       }
+
        drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
 }