i7core_edac: We need to use list_for_each_entry_safe to avoid errors
[safe/jmp/linux-2.6] / drivers / edac / i7core_edac.c
index f16aac2..2e4b0ab 100644 (file)
 #include <linux/mmzone.h>
 #include <linux/edac_mce.h>
 #include <linux/spinlock.h>
+#include <linux/smp.h>
+#include <asm/processor.h>
 
 #include "edac_core.h"
 
 /*
+ * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
+ * registers start at bus 255, and are not reported by BIOS.
+ * We currently find devices with only 2 sockets. In order to support more QPI
+ * Quick Path Interconnect, just increment this number.
+ */
+#define MAX_SOCKET_BUSES       2
+
+
+/*
  * Alter this version for the module when modifications are made
  */
 #define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
 #define EDAC_MOD_STR      "i7core_edac"
 
-/* HACK: temporary, just to enable all logs, for now */
-#undef debugf0
-#define debugf0(fmt, arg...)  edac_printk(KERN_INFO, "i7core", fmt, ##arg)
-
 /*
  * Debug macros
  */
   #define DIMM1_COR_ERR(r)                     (((r) >> 16) & 0x7fff)
   #define DIMM0_COR_ERR(r)                     ((r) & 0x7fff)
 
+/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
+#define MC_COR_ECC_CNT_0       0x80
+#define MC_COR_ECC_CNT_1       0x84
+#define MC_COR_ECC_CNT_2       0x88
+#define MC_COR_ECC_CNT_3       0x8c
+#define MC_COR_ECC_CNT_4       0x90
+#define MC_COR_ECC_CNT_5       0x94
+
+#define DIMM_TOP_COR_ERR(r)                    (((r) >> 16) & 0x7fff)
+#define DIMM_BOT_COR_ERR(r)                    ((r) & 0x7fff)
+
+
        /* OFFSETS for Devices 4,5 and 6 Function 0 */
 
 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
   #define REPEAT_EN            0x01
 
        /* OFFSETS for Devices 4,5 and 6 Function 1 */
+
 #define MC_DOD_CH_DIMM0                0x48
 #define MC_DOD_CH_DIMM1                0x4c
 #define MC_DOD_CH_DIMM2                0x50
 
 #define NUM_CHANS 3
 #define MAX_DIMMS 3            /* Max DIMMS per channel */
-#define NUM_SOCKETS 2          /* Max number of MC sockets */
 #define MAX_MCR_FUNC  4
 #define MAX_CHAN_FUNC 3
 
@@ -167,7 +186,6 @@ struct i7core_info {
 struct i7core_inject {
        int     enable;
 
-       u8      socket;
        u32     section;
        u32     type;
        u32     eccmask;
@@ -182,28 +200,42 @@ struct i7core_channel {
 };
 
 struct pci_id_descr {
-       int             dev;
-       int             func;
-       int             dev_id;
-       struct pci_dev  *pdev[NUM_SOCKETS];
+       int                     dev;
+       int                     func;
+       int                     dev_id;
+};
+
+struct i7core_dev {
+       struct list_head        list;
+       u8                      socket;
+       struct pci_dev          **pdev;
+       struct mem_ctl_info     *mci;
 };
 
 struct i7core_pvt {
-       struct pci_dev  *pci_noncore[NUM_SOCKETS];
-       struct pci_dev  *pci_mcr[NUM_SOCKETS][MAX_MCR_FUNC + 1];
-       struct pci_dev  *pci_ch[NUM_SOCKETS][NUM_CHANS][MAX_CHAN_FUNC + 1];
+       struct pci_dev  *pci_noncore;
+       struct pci_dev  *pci_mcr[MAX_MCR_FUNC + 1];
+       struct pci_dev  *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
+
+       struct i7core_dev *i7core_dev;
 
        struct i7core_info      info;
        struct i7core_inject    inject;
-       struct i7core_channel   channel[NUM_SOCKETS][NUM_CHANS];
+       struct i7core_channel   channel[NUM_CHANS];
 
-       int                     sockets; /* Number of sockets */
-       int                     channels; /* Number of active channels */
+       int             channels; /* Number of active channels */
 
-       int             ce_count_available[NUM_SOCKETS];
-                       /* ECC corrected errors counts per dimm */
-       unsigned long   ce_count[NUM_SOCKETS][MAX_DIMMS];
-       int             last_ce_count[NUM_SOCKETS][MAX_DIMMS];
+       int             ce_count_available;
+       int             csrow_map[NUM_CHANS][MAX_DIMMS];
+
+                       /* ECC corrected errors counts per udimm */
+       unsigned long   udimm_ce_count[MAX_DIMMS];
+       int             udimm_last_ce_count[MAX_DIMMS];
+                       /* ECC corrected errors counts per rdimm */
+       unsigned long   rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
+       int             rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
+
+       unsigned int    is_registered;
 
        /* mcelog glue */
        struct edac_mce         edac_mce;
@@ -212,22 +244,20 @@ struct i7core_pvt {
        spinlock_t              mce_lock;
 };
 
-/* Device name and register DID (Device ID) */
-struct i7core_dev_info {
-       const char *ctl_name;   /* name for this device */
-       u16 fsb_mapping_errors; /* DID for the branchmap,control */
-};
+/* Static vars */
+static LIST_HEAD(i7core_edac_list);
+static DEFINE_MUTEX(i7core_edac_lock);
 
 #define PCI_DESCR(device, function, device_id) \
        .dev = (device),                        \
        .func = (function),                     \
        .dev_id = (device_id)
 
-struct pci_id_descr pci_devs[] = {
+struct pci_id_descr pci_dev_descr[] = {
                /* Memory controller */
        { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
        { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
-       { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS)  }, /* if RDIMM is supported */
+       { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS)  }, /* if RDIMM */
        { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
 
                /* Channel 0 */
@@ -258,26 +288,16 @@ struct pci_id_descr pci_devs[] = {
        { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE)  },
 
 };
-#define N_DEVS ARRAY_SIZE(pci_devs)
+#define N_DEVS ARRAY_SIZE(pci_dev_descr)
 
 /*
  *     pci_device_id   table for which devices we are looking for
- * This should match the first device at pci_devs table
  */
 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
        {0,}                    /* 0 terminated list. */
 };
 
-
-/* Table of devices attributes supported by this driver */
-static const struct i7core_dev_info i7core_devs[] = {
-       {
-               .ctl_name = "i7 Core",
-               .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
-       },
-};
-
 static struct edac_pci_ctl_info *i7core_pci;
 
 /****************************************************************************
@@ -289,7 +309,7 @@ static struct edac_pci_ctl_info *i7core_pci;
 #define ECCx8(pvt)             ((pvt)->info.mc_control & (1 << 1))
 
        /* MC_STATUS bits */
-#define ECC_ENABLED(pvt)       ((pvt)->info.mc_status & (1 << 3))
+#define ECC_ENABLED(pvt)       ((pvt)->info.mc_status & (1 << 4))
 #define CH_DISABLED(pvt, ch)   ((pvt)->info.mc_status & (1 << ch))
 
        /* MC_MAX_DOD read functions */
@@ -330,21 +350,37 @@ static inline int numcol(u32 col)
        return cols[col & 0x3];
 }
 
+static struct i7core_dev *get_i7core_dev(u8 socket)
+{
+       struct i7core_dev *i7core_dev;
+
+       list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
+               if (i7core_dev->socket == socket)
+                       return i7core_dev;
+       }
+
+       return NULL;
+}
+
 /****************************************************************************
                        Memory check routines
  ****************************************************************************/
 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
                                          unsigned func)
 {
+       struct i7core_dev *i7core_dev = get_i7core_dev(socket);
        int i;
 
+       if (!i7core_dev)
+               return NULL;
+
        for (i = 0; i < N_DEVS; i++) {
-               if (!pci_devs[i].pdev[socket])
+               if (!i7core_dev->pdev[i])
                        continue;
 
-               if (PCI_SLOT(pci_devs[i].pdev[socket]->devfn) == slot &&
-                   PCI_FUNC(pci_devs[i].pdev[socket]->devfn) == func) {
-                       return pci_devs[i].pdev[socket];
+               if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
+                   PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
+                       return i7core_dev->pdev[i];
                }
        }
 
@@ -429,18 +465,19 @@ static int i7core_get_active_channels(u8 socket, unsigned *channels,
        return 0;
 }
 
-static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
+static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
 {
        struct i7core_pvt *pvt = mci->pvt_info;
        struct csrow_info *csr;
        struct pci_dev *pdev;
        int i, j;
+       u8 socket = pvt->i7core_dev->socket;
        unsigned long last_page = 0;
        enum edac_type mode;
        enum mem_type mtype;
 
        /* Get data from the MC register, function 0 */
-       pdev = pvt->pci_mcr[socket][0];
+       pdev = pvt->pci_mcr[0];
        if (!pdev)
                return -ENODEV;
 
@@ -487,10 +524,10 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
                }
 
                /* Devices 4-6 function 0 */
-               pci_read_config_dword(pvt->pci_ch[socket][i][0],
+               pci_read_config_dword(pvt->pci_ch[i][0],
                                MC_CHANNEL_DIMM_INIT_PARAMS, &data);
 
-               pvt->channel[socket][i].ranks = (data & QUAD_RANK_PRESENT) ?
+               pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
                                                4 : 2;
 
                if (data & REGISTERED_DIMM)
@@ -507,11 +544,11 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
 #endif
 
                /* Devices 4-6 function 1 */
-               pci_read_config_dword(pvt->pci_ch[socket][i][1],
+               pci_read_config_dword(pvt->pci_ch[i][1],
                                MC_DOD_CH_DIMM0, &dimm_dod[0]);
-               pci_read_config_dword(pvt->pci_ch[socket][i][1],
+               pci_read_config_dword(pvt->pci_ch[i][1],
                                MC_DOD_CH_DIMM1, &dimm_dod[1]);
-               pci_read_config_dword(pvt->pci_ch[socket][i][1],
+               pci_read_config_dword(pvt->pci_ch[i][1],
                                MC_DOD_CH_DIMM2, &dimm_dod[2]);
 
                debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
@@ -519,7 +556,7 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
                        i,
                        RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
                        data,
-                       pvt->channel[socket][i].ranks,
+                       pvt->channel[i].ranks,
                        (data & REGISTERED_DIMM) ? 'R' : 'U');
 
                for (j = 0; j < 3; j++) {
@@ -537,7 +574,7 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
                        /* DDR3 has 8 I/O banks */
                        size = (rows * cols * banks * ranks) >> (20 - 3);
 
-                       pvt->channel[socket][i].dimms++;
+                       pvt->channel[i].dimms++;
 
                        debugf0("\tdimm %d %d Mb offset: %x, "
                                "bank: %d, rank: %d, row: %#x, col: %#x\n",
@@ -565,6 +602,8 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
                        csr->channels[0].chan_idx = i;
                        csr->channels[0].ce_count = 0;
 
+                       pvt->csrow_map[i][j] = *csrow;
+
                        switch (banks) {
                        case 4:
                                csr->dtype = DEV_X4;
@@ -621,43 +660,16 @@ static int disable_inject(struct mem_ctl_info *mci)
 
        pvt->inject.enable = 0;
 
-       if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
+       if (!pvt->pci_ch[pvt->inject.channel][0])
                return -ENODEV;
 
-       pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
                                MC_CHANNEL_ERROR_INJECT, 0);
 
        return 0;
 }
 
 /*
- * i7core inject inject.socket
- *
- *     accept and store error injection inject.socket value
- */
-static ssize_t i7core_inject_socket_store(struct mem_ctl_info *mci,
-                                          const char *data, size_t count)
-{
-       struct i7core_pvt *pvt = mci->pvt_info;
-       unsigned long value;
-       int rc;
-
-       rc = strict_strtoul(data, 10, &value);
-       if ((rc < 0) || (value >= pvt->sockets))
-               return -EIO;
-
-       pvt->inject.socket = (u32) value;
-       return count;
-}
-
-static ssize_t i7core_inject_socket_show(struct mem_ctl_info *mci,
-                                             char *data)
-{
-       struct i7core_pvt *pvt = mci->pvt_info;
-       return sprintf(data, "%d\n", pvt->inject.socket);
-}
-
-/*
  * i7core inject inject.section
  *
  *     accept and store error injection inject.section value
@@ -878,7 +890,7 @@ static int write_and_test(struct pci_dev *dev, int where, u32 val)
 
        for (count = 0; count < 10; count++) {
                if (count)
-                       msleep (100);
+                       msleep(100);
                pci_write_config_dword(dev, where, val);
                pci_read_config_dword(dev, where, &read);
 
@@ -894,7 +906,6 @@ static int write_and_test(struct pci_dev *dev, int where, u32 val)
        return -EINVAL;
 }
 
-
 /*
  * This routine prepares the Memory Controller for error injection.
  * The error will be injected when some process tries to write to the
@@ -922,7 +933,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
        int  rc;
        long enable;
 
-       if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
+       if (!pvt->pci_ch[pvt->inject.channel][0])
                return 0;
 
        rc = strict_strtoul(data, 10, &enable);
@@ -940,7 +951,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
        if (pvt->inject.dimm < 0)
                mask |= 1L << 41;
        else {
-               if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
+               if (pvt->channel[pvt->inject.channel].dimms > 2)
                        mask |= (pvt->inject.dimm & 0x3L) << 35;
                else
                        mask |= (pvt->inject.dimm & 0x1L) << 36;
@@ -950,7 +961,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
        if (pvt->inject.rank < 0)
                mask |= 1L << 40;
        else {
-               if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
+               if (pvt->channel[pvt->inject.channel].dimms > 2)
                        mask |= (pvt->inject.rank & 0x1L) << 34;
                else
                        mask |= (pvt->inject.rank & 0x3L) << 34;
@@ -986,18 +997,18 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
                     (pvt->inject.type & 0x6) << (3 - 1);
 
        /* Unlock writes to registers - this register is write only */
-       pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
+       pci_write_config_dword(pvt->pci_noncore,
                               MC_CFG_CONTROL, 0x2);
 
-       write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       write_and_test(pvt->pci_ch[pvt->inject.channel][0],
                               MC_CHANNEL_ADDR_MATCH, mask);
-       write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       write_and_test(pvt->pci_ch[pvt->inject.channel][0],
                               MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
 
-       write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       write_and_test(pvt->pci_ch[pvt->inject.channel][0],
                               MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
 
-       write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       write_and_test(pvt->pci_ch[pvt->inject.channel][0],
                               MC_CHANNEL_ERROR_INJECT, injectmask);
 
        /*
@@ -1005,7 +1016,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
         * Without writing 8 to this register, errors aren't injected. Not sure
         * why.
         */
-       pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
+       pci_write_config_dword(pvt->pci_noncore,
                               MC_CFG_CONTROL, 8);
 
        debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
@@ -1022,7 +1033,7 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
        struct i7core_pvt *pvt = mci->pvt_info;
        u32 injectmask;
 
-       pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+       pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
                               MC_CHANNEL_ERROR_INJECT, &injectmask);
 
        debugf0("Inject error read: 0x%018x\n", injectmask);
@@ -1038,18 +1049,29 @@ static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
        unsigned i, count, total = 0;
        struct i7core_pvt *pvt = mci->pvt_info;
 
-       for (i = 0; i < pvt->sockets; i++) {
-               if (!pvt->ce_count_available[i])
-                       count = sprintf(data, "socket 0 data unavailable\n");
-               else
-                       count = sprintf(data, "socket %d, dimm0: %lu\n"
-                                             "dimm1: %lu\ndimm2: %lu\n",
-                                       i,
-                                       pvt->ce_count[i][0],
-                                       pvt->ce_count[i][1],
-                                       pvt->ce_count[i][2]);
+       if (!pvt->ce_count_available) {
+               count = sprintf(data, "data unavailable\n");
+               return 0;
+       }
+       if (!pvt->is_registered) {
+               count = sprintf(data, "all channels "
+                               "UDIMM0: %lu UDIMM1: %lu UDIMM2: %lu\n",
+                               pvt->udimm_ce_count[0],
+                               pvt->udimm_ce_count[1],
+                               pvt->udimm_ce_count[2]);
                data  += count;
                total += count;
+       } else {
+               for (i = 0; i < NUM_CHANS; i++) {
+                       count = sprintf(data, "channel %d RDIMM0: %lu "
+                                       "RDIMM1: %lu RDIMM2: %lu\n",
+                                       i,
+                                       pvt->rdimm_ce_count[i][0],
+                                       pvt->rdimm_ce_count[i][1],
+                                       pvt->rdimm_ce_count[i][2]);
+                       data  += count;
+                       total += count;
+               }
        }
 
        return total;
@@ -1061,13 +1083,6 @@ static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
 static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
        {
                .attr = {
-                       .name = "inject_socket",
-                       .mode = (S_IRUGO | S_IWUSR)
-               },
-               .show  = i7core_inject_socket_show,
-               .store = i7core_inject_socket_store,
-       }, {
-               .attr = {
                        .name = "inject_section",
                        .mode = (S_IRUGO | S_IWUSR)
                },
@@ -1109,6 +1124,7 @@ static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
                .show  = i7core_ce_regs_show,
                .store = NULL,
        },
+       { .attr = { .name = NULL } }
 };
 
 /****************************************************************************
@@ -1119,13 +1135,48 @@ static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
  *     i7core_put_devices      'put' all the devices that we have
  *                             reserved via 'get'
  */
-static void i7core_put_devices(void)
+static void i7core_put_devices(struct i7core_dev *i7core_dev)
 {
-       int i, j;
+       int i;
 
-       for (i = 0; i < NUM_SOCKETS; i++)
-               for (j = 0; j < N_DEVS; j++)
-                       pci_dev_put(pci_devs[j].pdev[i]);
+       debugf0(__FILE__ ": %s()\n", __func__);
+       for (i = 0; i < N_DEVS; i++) {
+               struct pci_dev *pdev = i7core_dev->pdev[i];
+               if (!pdev)
+                       continue;
+               debugf0("Removing dev %02x:%02x.%d\n",
+                       pdev->bus->number,
+                       PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+               pci_dev_put(pdev);
+       }
+       kfree(i7core_dev->pdev);
+       list_del(&i7core_dev->list);
+       kfree(i7core_dev);
+}
+
+static void i7core_put_all_devices(void)
+{
+       struct i7core_dev *i7core_dev, *tmp;
+
+       list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
+               i7core_put_devices(i7core_dev);
+}
+
+static void i7core_xeon_pci_fixup(void)
+{
+       struct pci_dev *pdev = NULL;
+       int i;
+       /*
+        * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
+        * aren't announced by acpi. So, we need to use a legacy scan probing
+        * to detect them
+        */
+       pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
+                             pci_dev_descr[0].dev_id, NULL);
+       if (unlikely(!pdev)) {
+               for (i = 0; i < MAX_SOCKET_BUSES; i++)
+                       pcibios_scan_specific_bus(255-i);
+       }
 }
 
 /*
@@ -1136,32 +1187,21 @@ static void i7core_put_devices(void)
  */
 int i7core_get_onedevice(struct pci_dev **prev, int devno)
 {
+       struct i7core_dev *i7core_dev;
+
        struct pci_dev *pdev = NULL;
        u8 bus = 0;
        u8 socket = 0;
 
        pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                             pci_devs[devno].dev_id, *prev);
-
-       /*
-        * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
-        * aren't announced by acpi. So, we need to use a legacy scan probing
-        * to detect them
-        */
-       if (unlikely(!pdev && !devno && !prev)) {
-               pcibios_scan_specific_bus(254);
-               pcibios_scan_specific_bus(255);
-
-               pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                                     pci_devs[devno].dev_id, *prev);
-       }
+                             pci_dev_descr[devno].dev_id, *prev);
 
        /*
         * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
         * is at addr 8086:2c40, instead of 8086:2c41. So, we need
         * to probe for the alternate address in case of failure
         */
-       if (pci_devs[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
+       if (pci_dev_descr[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
                                      PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
 
@@ -1175,15 +1215,15 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno)
                 * Dev 3 function 2 only exists on chips with RDIMMs
                 * so, it is ok to not found it
                 */
-               if ((pci_devs[devno].dev == 3) && (pci_devs[devno].func == 2)) {
+               if ((pci_dev_descr[devno].dev == 3) && (pci_dev_descr[devno].func == 2)) {
                        *prev = pdev;
                        return 0;
                }
 
                i7core_printk(KERN_ERR,
                        "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
-                       pci_devs[devno].dev, pci_devs[devno].func,
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+                       pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
+                       PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
 
                /* End of list, leave */
                return -ENODEV;
@@ -1195,37 +1235,40 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno)
        else
                socket = 255 - bus;
 
-       if (socket >= NUM_SOCKETS) {
-               i7core_printk(KERN_ERR,
-                       "Unexpected socket for "
-                       "dev %02x:%02x.%d PCI ID %04x:%04x\n",
-                       bus, pci_devs[devno].dev, pci_devs[devno].func,
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
-               pci_dev_put(pdev);
-               return -ENODEV;
+       i7core_dev = get_i7core_dev(socket);
+       if (!i7core_dev) {
+               i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
+               if (!i7core_dev)
+                       return -ENOMEM;
+               i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * N_DEVS,
+                                          GFP_KERNEL);
+               if (!i7core_dev->pdev)
+                       return -ENOMEM;
+               i7core_dev->socket = socket;
+               list_add_tail(&i7core_dev->list, &i7core_edac_list);
        }
 
-       if (pci_devs[devno].pdev[socket]) {
+       if (i7core_dev->pdev[devno]) {
                i7core_printk(KERN_ERR,
                        "Duplicated device for "
                        "dev %02x:%02x.%d PCI ID %04x:%04x\n",
-                       bus, pci_devs[devno].dev, pci_devs[devno].func,
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+                       bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
+                       PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
                pci_dev_put(pdev);
                return -ENODEV;
        }
 
-       pci_devs[devno].pdev[socket] = pdev;
+       i7core_dev->pdev[devno] = pdev;
 
        /* Sanity check */
-       if (unlikely(PCI_SLOT(pdev->devfn) != pci_devs[devno].dev ||
-                       PCI_FUNC(pdev->devfn) != pci_devs[devno].func)) {
+       if (unlikely(PCI_SLOT(pdev->devfn) != pci_dev_descr[devno].dev ||
+                       PCI_FUNC(pdev->devfn) != pci_dev_descr[devno].func)) {
                i7core_printk(KERN_ERR,
                        "Device PCI ID %04x:%04x "
                        "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id,
+                       PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id,
                        bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
-                       bus, pci_devs[devno].dev, pci_devs[devno].func);
+                       bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func);
                return -ENODEV;
        }
 
@@ -1234,16 +1277,15 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno)
                i7core_printk(KERN_ERR,
                        "Couldn't enable "
                        "dev %02x:%02x.%d PCI ID %04x:%04x\n",
-                       bus, pci_devs[devno].dev, pci_devs[devno].func,
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+                       bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
+                       PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
                return -ENODEV;
        }
 
-       i7core_printk(KERN_INFO,
-                       "Registered socket %d "
-                       "dev %02x:%02x.%d PCI ID %04x:%04x\n",
-                       socket, bus, pci_devs[devno].dev, pci_devs[devno].func,
-                       PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+       debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
+               socket, bus, pci_dev_descr[devno].dev,
+               pci_dev_descr[devno].func,
+               PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
 
        *prev = pdev;
 
@@ -1259,45 +1301,54 @@ static int i7core_get_devices(void)
                pdev = NULL;
                do {
                        if (i7core_get_onedevice(&pdev, i) < 0) {
-                               i7core_put_devices();
+                               i7core_put_all_devices();
                                return -ENODEV;
                        }
                } while (pdev);
        }
+
        return 0;
 }
 
-static int mci_bind_devs(struct mem_ctl_info *mci)
+static int mci_bind_devs(struct mem_ctl_info *mci,
+                        struct i7core_dev *i7core_dev)
 {
        struct i7core_pvt *pvt = mci->pvt_info;
        struct pci_dev *pdev;
-       int i, j, func, slot;
+       int i, func, slot;
 
-       for (i = 0; i < pvt->sockets; i++) {
-               for (j = 0; j < N_DEVS; j++) {
-                       pdev = pci_devs[j].pdev[i];
-                       if (!pdev)
-                               continue;
+       /* Associates i7core_dev and mci for future usage */
+       pvt->i7core_dev = i7core_dev;
+       i7core_dev->mci = mci;
 
-                       func = PCI_FUNC(pdev->devfn);
-                       slot = PCI_SLOT(pdev->devfn);
-                       if (slot == 3) {
-                               if (unlikely(func > MAX_MCR_FUNC))
-                                       goto error;
-                               pvt->pci_mcr[i][func] = pdev;
-                       } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
-                               if (unlikely(func > MAX_CHAN_FUNC))
-                                       goto error;
-                               pvt->pci_ch[i][slot - 4][func] = pdev;
-                       } else if (!slot && !func)
-                               pvt->pci_noncore[i] = pdev;
-                       else
+       pvt->is_registered = 0;
+       for (i = 0; i < N_DEVS; i++) {
+               pdev = i7core_dev->pdev[i];
+               if (!pdev)
+                       continue;
+
+               func = PCI_FUNC(pdev->devfn);
+               slot = PCI_SLOT(pdev->devfn);
+               if (slot == 3) {
+                       if (unlikely(func > MAX_MCR_FUNC))
                                goto error;
+                       pvt->pci_mcr[func] = pdev;
+               } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
+                       if (unlikely(func > MAX_CHAN_FUNC))
+                               goto error;
+                       pvt->pci_ch[slot - 4][func] = pdev;
+               } else if (!slot && !func)
+                       pvt->pci_noncore = pdev;
+               else
+                       goto error;
 
-                       debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
-                               PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
-                               pdev, i);
-               }
+               debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
+                       PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
+                       pdev, i7core_dev->socket);
+
+               if (PCI_SLOT(pdev->devfn) == 3 &&
+                       PCI_FUNC(pdev->devfn) == 2)
+                       pvt->is_registered = 1;
        }
 
        return 0;
@@ -1312,6 +1363,103 @@ error:
 /****************************************************************************
                        Error check routines
  ****************************************************************************/
+static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
+                                        int chan, int dimm, int add)
+{
+       char *msg;
+       struct i7core_pvt *pvt = mci->pvt_info;
+       int row = pvt->csrow_map[chan][dimm], i;
+
+       for (i = 0; i < add; i++) {
+               msg = kasprintf(GFP_KERNEL, "Corrected error "
+                               "(Socket=%d channel=%d dimm=%d)",
+                               pvt->i7core_dev->socket, chan, dimm);
+
+               edac_mc_handle_fbd_ce(mci, row, 0, msg);
+               kfree (msg);
+       }
+}
+
+static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
+                       int chan, int new0, int new1, int new2)
+{
+       struct i7core_pvt *pvt = mci->pvt_info;
+       int add0 = 0, add1 = 0, add2 = 0;
+       /* Updates CE counters if it is not the first time here */
+       if (pvt->ce_count_available) {
+               /* Updates CE counters */
+
+               add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
+               add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
+               add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
+
+               if (add2 < 0)
+                       add2 += 0x7fff;
+               pvt->rdimm_ce_count[chan][2] += add2;
+
+               if (add1 < 0)
+                       add1 += 0x7fff;
+               pvt->rdimm_ce_count[chan][1] += add1;
+
+               if (add0 < 0)
+                       add0 += 0x7fff;
+               pvt->rdimm_ce_count[chan][0] += add0;
+       } else
+               pvt->ce_count_available = 1;
+
+       /* Store the new values */
+       pvt->rdimm_last_ce_count[chan][2] = new2;
+       pvt->rdimm_last_ce_count[chan][1] = new1;
+       pvt->rdimm_last_ce_count[chan][0] = new0;
+
+       /*updated the edac core */
+       if (add0 != 0)
+               i7core_rdimm_update_csrow(mci, chan, 0, add0);
+       if (add1 != 0)
+               i7core_rdimm_update_csrow(mci, chan, 1, add1);
+       if (add2 != 0)
+               i7core_rdimm_update_csrow(mci, chan, 2, add2);
+
+}
+
+static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
+{
+       struct i7core_pvt *pvt = mci->pvt_info;
+       u32 rcv[3][2];
+       int i, new0, new1, new2;
+
+       /*Read DEV 3: FUN 2:  MC_COR_ECC_CNT regs directly*/
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
+                                                               &rcv[0][0]);
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
+                                                               &rcv[0][1]);
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
+                                                               &rcv[1][0]);
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
+                                                               &rcv[1][1]);
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
+                                                               &rcv[2][0]);
+       pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
+                                                               &rcv[2][1]);
+       for (i = 0 ; i < 3; i++) {
+               debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
+                       (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
+               /*if the channel has 3 dimms*/
+               if (pvt->channel[i].dimms > 2) {
+                       new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
+                       new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
+                       new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
+               } else {
+                       new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
+                                       DIMM_BOT_COR_ERR(rcv[i][0]);
+                       new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
+                                       DIMM_BOT_COR_ERR(rcv[i][1]);
+                       new2 = 0;
+               }
+
+               i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
+       }
+}
 
 /* This function is based on the device 3 function 4 registers as described on:
  * Intel Xeon Processor 5500 Series Datasheet Volume 2
@@ -1319,59 +1467,58 @@ error:
  * also available at:
  *     http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  */
-static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
+static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
 {
        struct i7core_pvt *pvt = mci->pvt_info;
        u32 rcv1, rcv0;
        int new0, new1, new2;
 
-       if (!pvt->pci_mcr[socket][4]) {
-               debugf0("%s MCR registers not found\n",__func__);
+       if (!pvt->pci_mcr[4]) {
+               debugf0("%s MCR registers not found\n", __func__);
                return;
        }
 
-       /* Corrected error reads */
-       pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
-       pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
+       /* Corrected test errors */
+       pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
+       pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
 
        /* Store the new values */
        new2 = DIMM2_COR_ERR(rcv1);
        new1 = DIMM1_COR_ERR(rcv0);
        new0 = DIMM0_COR_ERR(rcv0);
 
-#if 0
-       debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
-               (pvt->ce_count_available ? "UPDATE" : "READ"),
-               rcv1, rcv0, new0, new1, new2);
-#endif
-
        /* Updates CE counters if it is not the first time here */
-       if (pvt->ce_count_available[socket]) {
+       if (pvt->ce_count_available) {
                /* Updates CE counters */
                int add0, add1, add2;
 
-               add2 = new2 - pvt->last_ce_count[socket][2];
-               add1 = new1 - pvt->last_ce_count[socket][1];
-               add0 = new0 - pvt->last_ce_count[socket][0];
+               add2 = new2 - pvt->udimm_last_ce_count[2];
+               add1 = new1 - pvt->udimm_last_ce_count[1];
+               add0 = new0 - pvt->udimm_last_ce_count[0];
 
                if (add2 < 0)
                        add2 += 0x7fff;
-               pvt->ce_count[socket][2] += add2;
+               pvt->udimm_ce_count[2] += add2;
 
                if (add1 < 0)
                        add1 += 0x7fff;
-               pvt->ce_count[socket][1] += add1;
+               pvt->udimm_ce_count[1] += add1;
 
                if (add0 < 0)
                        add0 += 0x7fff;
-               pvt->ce_count[socket][0] += add0;
+               pvt->udimm_ce_count[0] += add0;
+
+               if (add0 | add1 | add2)
+                       i7core_printk(KERN_ERR, "New Corrected error(s): "
+                                     "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
+                                     add0, add1, add2);
        } else
-               pvt->ce_count_available[socket] = 1;
+               pvt->ce_count_available = 1;
 
        /* Store the new values */
-       pvt->last_ce_count[socket][2] = new2;
-       pvt->last_ce_count[socket][1] = new1;
-       pvt->last_ce_count[socket][0] = new0;
+       pvt->udimm_last_ce_count[2] = new2;
+       pvt->udimm_last_ce_count[1] = new1;
+       pvt->udimm_last_ce_count[0] = new0;
 }
 
 /*
@@ -1390,6 +1537,7 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
 static void i7core_mce_output_error(struct mem_ctl_info *mci,
                                    struct mce *m)
 {
+       struct i7core_pvt *pvt = mci->pvt_info;
        char *type, *optype, *err, *msg;
        unsigned long error = m->status & 0x1ff0000l;
        u32 optypenum = (m->status >> 4) & 0x07;
@@ -1398,6 +1546,7 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
        u32 channel = (m->misc >> 18) & 0x3;
        u32 syndrome = m->misc >> 32;
        u32 errnum = find_first_bit(&error, 32);
+       int csrow;
 
        if (m->mcgstatus & 1)
                type = "FATAL";
@@ -1405,24 +1554,24 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
                type = "NON_FATAL";
 
        switch (optypenum) {
-               case 0:
-                       optype = "generic undef request";
-                       break;
-               case 1:
-                       optype = "read error";
-                       break;
-               case 2:
-                       optype = "write error";
-                       break;
-               case 3:
-                       optype = "addr/cmd error";
-                       break;
-               case 4:
-                       optype = "scrubbing error";
-                       break;
-               default:
-                       optype = "reserved";
-                       break;
+       case 0:
+               optype = "generic undef request";
+               break;
+       case 1:
+               optype = "read error";
+               break;
+       case 2:
+               optype = "write error";
+               break;
+       case 3:
+               optype = "addr/cmd error";
+               break;
+       case 4:
+               optype = "scrubbing error";
+               break;
+       default:
+               optype = "reserved";
+               break;
        }
 
        switch (errnum) {
@@ -1459,7 +1608,7 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
 
        /* FIXME: should convert addr into bank and rank information */
        msg = kasprintf(GFP_ATOMIC,
-               "%s (addr = 0x%08llx, socket=%d, Dimm=%d, Channel=%d, "
+               "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
                "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
                type, (long long) m->addr, m->cpu, dimm, channel,
                syndrome, core_err_cnt, (long long)m->status,
@@ -1467,9 +1616,15 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
 
        debugf0("%s", msg);
 
+       csrow = pvt->csrow_map[channel][dimm];
+
        /* Call the helper to output message */
-       edac_mc_handle_fbd_ue(mci, 0 /* FIXME: should be rank here */,
-                             0, 0 /* FIXME: should be channel here */, msg);
+       if (m->mcgstatus & 1)
+               edac_mc_handle_fbd_ue(mci, csrow, 0,
+                               0 /* FIXME: should be channel here */, msg);
+       else if (!pvt->is_registered)
+               edac_mc_handle_fbd_ce(mci, csrow,
+                               0 /* FIXME: should be channel here */, msg);
 
        kfree(msg);
 }
@@ -1490,12 +1645,14 @@ static void i7core_check_error(struct mem_ctl_info *mci)
        spin_lock_irqsave(&pvt->mce_lock, flags);
        if (pvt->mce_count) {
                m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC);
+
                if (m) {
                        count = pvt->mce_count;
                        memcpy(m, &pvt->mce_entry, sizeof(*m) * count);
                }
                pvt->mce_count = 0;
        }
+
        spin_unlock_irqrestore(&pvt->mce_lock, flags);
 
        /* proccess mcelog errors */
@@ -1505,8 +1662,10 @@ static void i7core_check_error(struct mem_ctl_info *mci)
        kfree(m);
 
        /* check memory count errors */
-       for (i = 0; i < pvt->sockets; i++)
-               check_mc_test_err(mci, i);
+       if (!pvt->is_registered)
+               i7core_udimm_check_mc_ecc_err(mci);
+       else
+               i7core_rdimm_check_mc_ecc_err(mci);
 }
 
 /*
@@ -1532,6 +1691,15 @@ static int i7core_mce_check_error(void *priv, struct mce *mce)
        if (mce->bank != 8)
                return 0;
 
+       /* Only handle if it is the right mc controller */
+       if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) {
+               debugf0("mc%d: ignoring mce log for socket %d. "
+                       "Another mc should get it.\n",
+                       pvt->i7core_dev->socket,
+                       cpu_data(mce->cpu).phys_proc_id);
+               return 0;
+       }
+
        spin_lock_irqsave(&pvt->mce_lock, flags);
        if (pvt->mce_count < MCE_LOG_LEN) {
                memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
@@ -1547,67 +1715,27 @@ static int i7core_mce_check_error(void *priv, struct mce *mce)
        return 1;
 }
 
-/*
- *     i7core_probe    Probe for ONE instance of device to see if it is
- *                     present.
- *     return:
- *             0 for FOUND a device
- *             < 0 for error code
- */
-static int __devinit i7core_probe(struct pci_dev *pdev,
-                                 const struct pci_device_id *id)
+static int i7core_register_mci(struct i7core_dev *i7core_dev,
+                              int num_channels, int num_csrows)
 {
        struct mem_ctl_info *mci;
        struct i7core_pvt *pvt;
-       int num_channels = 0;
-       int num_csrows = 0;
        int csrow = 0;
-       int dev_idx = id->driver_data;
-       int rc, i;
-       u8 sockets;
-
-       if (unlikely(dev_idx >= ARRAY_SIZE(i7core_devs)))
-               return -EINVAL;
-
-       /* get the pci devices we want to reserve for our use */
-       rc = i7core_get_devices();
-       if (unlikely(rc < 0))
-               return rc;
-
-       sockets = 1;
-       for (i = NUM_SOCKETS - 1; i > 0; i--)
-               if (pci_devs[0].pdev[i]) {
-                       sockets = i + 1;
-                       break;
-               }
-
-       for (i = 0; i < sockets; i++) {
-               int channels;
-               int csrows;
-
-               /* Check the number of active and not disabled channels */
-               rc = i7core_get_active_channels(i, &channels, &csrows);
-               if (unlikely(rc < 0))
-                       goto fail0;
-
-               num_channels += channels;
-               num_csrows += csrows;
-       }
+       int rc;
 
        /* allocate a new MC control structure */
-       mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
-       if (unlikely(!mci)) {
-               rc = -ENOMEM;
-               goto fail0;
-       }
+       mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
+                           i7core_dev->socket);
+       if (unlikely(!mci))
+               return -ENOMEM;
 
        debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
 
-       mci->dev = &pdev->dev;  /* record ptr to the generic device */
+       /* record ptr to the generic device */
+       mci->dev = &i7core_dev->pdev[0]->dev;
+
        pvt = mci->pvt_info;
        memset(pvt, 0, sizeof(*pvt));
-       pvt->sockets = sockets;
-       mci->mc_idx = 0;
 
        /*
         * FIXME: how to handle RDDR3 at MCI level? It is possible to have
@@ -1619,21 +1747,21 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
        mci->edac_cap = EDAC_FLAG_NONE;
        mci->mod_name = "i7core_edac.c";
        mci->mod_ver = I7CORE_REVISION;
-       mci->ctl_name = i7core_devs[dev_idx].ctl_name;
-       mci->dev_name = pci_name(pdev);
+       mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
+                                 i7core_dev->socket);
+       mci->dev_name = pci_name(i7core_dev->pdev[0]);
        mci->ctl_page_to_phys = NULL;
        mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
        /* Set the function pointer to an actual operation function */
        mci->edac_check = i7core_check_error;
 
        /* Store pci devices at mci for faster access */
-       rc = mci_bind_devs(mci);
+       rc = mci_bind_devs(mci, i7core_dev);
        if (unlikely(rc < 0))
-               goto fail1;
+               goto fail;
 
        /* Get dimm basic config */
-       for (i = 0; i < sockets; i++)
-               get_dimm_config(mci, &csrow, i);
+       get_dimm_config(mci, &csrow);
 
        /* add this new MC control structure to EDAC's list of MCs */
        if (unlikely(edac_mc_add_mc(mci))) {
@@ -1644,11 +1772,12 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
                 */
 
                rc = -EINVAL;
-               goto fail1;
+               goto fail;
        }
 
        /* allocating generic PCI control info */
-       i7core_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
+       i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
+                                                EDAC_MOD_STR);
        if (unlikely(!i7core_pci)) {
                printk(KERN_WARNING
                        "%s(): Unable to create PCI control\n",
@@ -1672,21 +1801,66 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
        spin_lock_init(&pvt->mce_lock);
 
        rc = edac_mce_register(&pvt->edac_mce);
-       if (unlikely (rc < 0)) {
+       if (unlikely(rc < 0)) {
                debugf0("MC: " __FILE__
                        ": %s(): failed edac_mce_register()\n", __func__);
-               goto fail1;
+       }
+
+fail:
+       edac_mc_free(mci);
+       return rc;
+}
+
+/*
+ *     i7core_probe    Probe for ONE instance of device to see if it is
+ *                     present.
+ *     return:
+ *             0 for FOUND a device
+ *             < 0 for error code
+ */
+static int __devinit i7core_probe(struct pci_dev *pdev,
+                                 const struct pci_device_id *id)
+{
+       int dev_idx = id->driver_data;
+       int rc;
+       struct i7core_dev *i7core_dev;
+
+       /*
+        * All memory controllers are allocated at the first pass.
+        */
+       if (unlikely(dev_idx >= 1))
+               return -EINVAL;
+
+       /* get the pci devices we want to reserve for our use */
+       mutex_lock(&i7core_edac_lock);
+       rc = i7core_get_devices();
+       if (unlikely(rc < 0))
+               goto fail0;
+
+       list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
+               int channels;
+               int csrows;
+
+               /* Check the number of active and not disabled channels */
+               rc = i7core_get_active_channels(i7core_dev->socket,
+                                               &channels, &csrows);
+               if (unlikely(rc < 0))
+                       goto fail1;
+
+               rc = i7core_register_mci(i7core_dev, channels, csrows);
+               if (unlikely(rc < 0))
+                       goto fail1;
        }
 
        i7core_printk(KERN_INFO, "Driver loaded.\n");
 
+       mutex_unlock(&i7core_edac_lock);
        return 0;
 
 fail1:
-       edac_mc_free(mci);
-
+       i7core_put_all_devices();
 fail0:
-       i7core_put_devices();
+       mutex_unlock(&i7core_edac_lock);
        return rc;
 }
 
@@ -1697,26 +1871,39 @@ fail0:
 static void __devexit i7core_remove(struct pci_dev *pdev)
 {
        struct mem_ctl_info *mci;
-       struct i7core_pvt *pvt;
+       struct i7core_dev *i7core_dev, *tmp;
 
        debugf0(__FILE__ ": %s()\n", __func__);
 
        if (i7core_pci)
                edac_pci_release_generic_ctl(i7core_pci);
 
+       /*
+        * we have a trouble here: pdev value for removal will be wrong, since
+        * it will point to the X58 register used to detect that the machine
+        * is a Nehalem or upper design. However, due to the way several PCI
+        * devices are grouped together to provide MC functionality, we need
+        * to use a different method for releasing the devices
+        */
 
-       mci = edac_mc_del_mc(&pdev->dev);
-       if (!mci)
-               return;
-
-       /* Unregisters on edac_mce in order to receive memory errors */
-       pvt = mci->pvt_info;
-       edac_mce_unregister(&pvt->edac_mce);
-
-       /* retrieve references to resources, and free those resources */
-       i7core_put_devices();
-
-       edac_mc_free(mci);
+       mutex_lock(&i7core_edac_lock);
+       list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
+               mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
+               if (mci) {
+                       struct i7core_pvt *pvt = mci->pvt_info;
+
+                       i7core_dev = pvt->i7core_dev;
+                       edac_mce_unregister(&pvt->edac_mce);
+                       kfree(mci->ctl_name);
+                       edac_mc_free(mci);
+                       i7core_put_devices(i7core_dev);
+               } else {
+                       i7core_printk(KERN_ERR,
+                                     "Couldn't find mci for socket %d\n",
+                                     i7core_dev->socket);
+               }
+       }
+       mutex_unlock(&i7core_edac_lock);
 }
 
 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
@@ -1745,9 +1932,17 @@ static int __init i7core_init(void)
        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
        opstate_init();
 
+       i7core_xeon_pci_fixup();
+
        pci_rc = pci_register_driver(&i7core_driver);
 
-       return (pci_rc < 0) ? pci_rc : 0;
+       if (pci_rc >= 0)
+               return 0;
+
+       i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
+                     pci_rc);
+
+       return pci_rc;
 }
 
 /*