ALSA: pcm: fix the fix of the runtime->boundary calculation

[safe/jmp/linux-2.6] / drivers / edac / edac_mce_amd.c

diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
index c693fcc..97e64bc 100644 (file)
--- a/drivers/edac/edac_mce_amd.c
+++ b/drivers/edac/edac_mce_amd.c
@@ -294,11 +294,16 @@ wrong_ls_mce:
 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
 {
        u32 ec  = ERROR_CODE(regs->nbsl);
-       u32 xec = EXT_ERROR_CODE(regs->nbsl);
 
        if (!handle_errors)
                return;
 
+       /*
+        * GART TLB error reporting is disabled by default. Bail out early.
+        */
+       if (TLB_ERROR(ec) && !report_gart_errors)
+               return;
+
        pr_emerg(" Northbridge Error, node %d", node_id);
 
        /*
@@ -310,11 +315,15 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
                if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
                        pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
        } else {
-               pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
-       }
+               u8 assoc_cpus = regs->nbsh & 0xf;
+
+               if (assoc_cpus > 0)
+                       pr_cont(", core: %d", fls(assoc_cpus) - 1);
 
+               pr_cont("\n");
+       }
 
-       pr_emerg("%s.\n", EXT_ERR_MSG(xec));
+       pr_emerg("%s.\n", EXT_ERR_MSG(regs->nbsl));
 
        if (BUS_ERROR(ec) && nb_bus_decoder)
                nb_bus_decoder(node_id, regs);
@@ -333,21 +342,6 @@ static void amd_decode_fr_mce(u64 mc5_status)
 static inline void amd_decode_err_code(unsigned int ec)
 {
        if (TLB_ERROR(ec)) {
-               /*
-                * GART errors are intended to help graphics driver developers
-                * to detect bad GART PTEs. It is recommended by AMD to disable
-                * GART table walk error reporting by default[1] (currently
-                * being disabled in mce_cpu_quirks()) and according to the
-                * comment in mce_cpu_quirks(), such GART errors can be
-                * incorrectly triggered. We may see these errors anyway and
-                * unless requested by the user, they won't be reported.
-                *
-                * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
-                *     AMD NPT family 0Fh processors
-                */
-               if (!report_gart_errors)
-                       return;
-
                pr_emerg(" Transaction: %s, Cache Level %s\n",
                         TT_MSG(ec), LL_MSG(ec));
        } else if (MEM_ERROR(ec)) {
@@ -379,7 +373,7 @@ static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
                 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
 
        /* do the two bits[14:13] together */
-       ecc = m->status & (3ULL << 45);
+       ecc = (m->status >> 45) & 0x3;
        if (ecc)
                pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));