drivers/edac: add mips and ppc visibility

[safe/jmp/linux-2.6] / drivers / edac / amd76x_edac.c

diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c
index 00d5254..1c1e02e 100644 (file)
--- a/drivers/edac/amd76x_edac.c
+++ b/drivers/edac/amd76x_edac.c
@@ -86,13 +86,13 @@ struct amd76x_dev_info {
 
 static const struct amd76x_dev_info amd76x_devs[] = {
        [AMD761] = {
-               .ctl_name = "AMD761"
-       },
+               .ctl_name = "AMD761"},
        [AMD762] = {
-               .ctl_name = "AMD762"
-       },
+               .ctl_name = "AMD762"},
 };
 
+static struct edac_pci_ctl_info *amd76x_pci;
+
 /**
  *     amd76x_get_error_info   -       fetch error information
  *     @mci: Memory controller
@@ -102,21 +102,21 @@ static const struct amd76x_dev_info amd76x_devs[] = {
  *     on the chip so that further errors will be reported
  */
 static void amd76x_get_error_info(struct mem_ctl_info *mci,
-               struct amd76x_error_info *info)
+                               struct amd76x_error_info *info)
 {
        struct pci_dev *pdev;
 
        pdev = to_pci_dev(mci->dev);
        pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
-                               &info->ecc_mode_status);
+                       &info->ecc_mode_status);
 
        if (info->ecc_mode_status & BIT(8))
                pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
-                               (u32) BIT(8), (u32) BIT(8));
+                                (u32) BIT(8), (u32) BIT(8));
 
        if (info->ecc_mode_status & BIT(9))
                pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
-                               (u32) BIT(9), (u32) BIT(9));
+                                (u32) BIT(9), (u32) BIT(9));
 }
 
 /**
@@ -130,7 +130,8 @@ static void amd76x_get_error_info(struct mem_ctl_info *mci,
  *     then attempt to handle and clean up after the error
  */
 static int amd76x_process_error_info(struct mem_ctl_info *mci,
-               struct amd76x_error_info *info, int handle_errors)
+                               struct amd76x_error_info *info,
+                               int handle_errors)
 {
        int error_found;
        u32 row;
@@ -138,7 +139,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
        error_found = 0;
 
        /*
-        *      Check for an uncorrectable error
+        *      Check for an uncorrectable error
         */
        if (info->ecc_mode_status & BIT(8)) {
                error_found = 1;
@@ -146,12 +147,12 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
                if (handle_errors) {
                        row = (info->ecc_mode_status >> 4) & 0xf;
                        edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
-                               row, mci->ctl_name);
+                                       row, mci->ctl_name);
                }
        }
 
        /*
-        *      Check for a correctable error
+        *      Check for a correctable error
         */
        if (info->ecc_mode_status & BIT(9)) {
                error_found = 1;
@@ -159,7 +160,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
                if (handle_errors) {
                        row = info->ecc_mode_status & 0xf;
                        edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
-                               0, row, 0, mci->ctl_name);
+                                       0, row, 0, mci->ctl_name);
                }
        }
 
@@ -182,7 +183,7 @@ static void amd76x_check(struct mem_ctl_info *mci)
 }
 
 static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
-               enum edac_type edac_mode)
+                       enum edac_type edac_mode)
 {
        struct csrow_info *csrow;
        u32 mba, mba_base, mba_mask, dms;
@@ -193,8 +194,7 @@ static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 
                /* find the DRAM Chip Select Base address and mask */
                pci_read_config_dword(pdev,
-                                     AMD76X_MEM_BASE_ADDR + (index * 4),
-                                     &mba);
+                               AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
 
                if (!(mba & BIT(0)))
                        continue;
@@ -249,24 +249,36 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
        mci->mtype_cap = MEM_FLAG_RDDR;
        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
        mci->edac_cap = ems_mode ?
-                       (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
+               (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
        mci->mod_name = EDAC_MOD_STR;
        mci->mod_ver = AMD76X_REVISION;
        mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
+       mci->dev_name = pci_name(pdev);
        mci->edac_check = amd76x_check;
        mci->ctl_page_to_phys = NULL;
 
        amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
-       amd76x_get_error_info(mci, &discard);  /* clear counters */
+       amd76x_get_error_info(mci, &discard);   /* clear counters */
 
        /* Here we assume that we will never see multiple instances of this
         * type of memory controller.  The ID is therefore hardcoded to 0.
         */
-       if (edac_mc_add_mc(mci,0)) {
+       if (edac_mc_add_mc(mci, 0)) {
                debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
                goto fail;
        }
 
+       /* allocating generic PCI control info */
+       amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
+       if (!amd76x_pci) {
+               printk(KERN_WARNING
+                       "%s(): Unable to create PCI control\n",
+                       __func__);
+               printk(KERN_WARNING
+                       "%s(): PCI error report via EDAC not setup\n",
+                       __func__);
+       }
+
        /* get this far and it's successful */
        debugf3("%s(): success\n", __func__);
        return 0;
@@ -278,7 +290,7 @@ fail:
 
 /* returns count (>= 0), or negative on error */
 static int __devinit amd76x_init_one(struct pci_dev *pdev,
-               const struct pci_device_id *ent)
+                               const struct pci_device_id *ent)
 {
        debugf0("%s()\n", __func__);
 
@@ -300,6 +312,9 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
 
        debugf0("%s()\n", __func__);
 
+       if (amd76x_pci)
+               edac_pci_release_generic_ctl(amd76x_pci);
+
        if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
                return;
 
@@ -308,16 +323,14 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
 
 static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
        {
-               PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-               AMD762
-       },
+        PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+        AMD762},
        {
-               PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
-               AMD761
-       },
+        PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+        AMD761},
        {
-               0,
-       }       /* 0 terminated list. */
+        0,
+        }                      /* 0 terminated list. */
 };
 
 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);