x86: mce: macros to compute banks MSRs

[safe/jmp/linux-2.6] / drivers / dma / ioatdma.h

diff --git a/drivers/dma/ioatdma.h b/drivers/dma/ioatdma.h
index 312353d..a52ff4b 100644 (file)
--- a/drivers/dma/ioatdma.h
+++ b/drivers/dma/ioatdma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
+ * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
@@ -26,69 +26,76 @@
 #include <linux/init.h>
 #include <linux/dmapool.h>
 #include <linux/cache.h>
+#include <linux/pci_ids.h>
+#include <net/tcp.h>
 
-#define PCI_DEVICE_ID_INTEL_IOAT       0x1a38
+#define IOAT_DMA_VERSION  "3.64"
+
+enum ioat_interrupt {
+       none = 0,
+       msix_multi_vector = 1,
+       msix_single_vector = 2,
+       msi = 3,
+       intx = 4,
+};
 
 #define IOAT_LOW_COMPLETION_MASK       0xffffffc0
+#define IOAT_DMA_DCA_ANY_CPU           ~0
+#define IOAT_WATCHDOG_PERIOD           (2 * HZ)
 
-extern struct list_head dma_device_list;
-extern struct list_head dma_client_list;
 
 /**
- * struct ioat_device - internal representation of a IOAT device
+ * struct ioatdma_device - internal representation of a IOAT device
  * @pdev: PCI-Express device
  * @reg_base: MMIO register space base address
  * @dma_pool: for allocating DMA descriptors
  * @common: embedded struct dma_device
- * @msi: Message Signaled Interrupt number
+ * @version: version of ioatdma device
+ * @irq_mode: which style irq to use
+ * @msix_entries: irq handlers
+ * @idx: per channel data
  */
 
-struct ioat_device {
+struct ioatdma_device {
        struct pci_dev *pdev;
-       void *reg_base;
+       void __iomem *reg_base;
        struct pci_pool *dma_pool;
        struct pci_pool *completion_pool;
-
        struct dma_device common;
-       u8 msi;
+       u8 version;
+       enum ioat_interrupt irq_mode;
+       struct delayed_work work;
+       struct msix_entry msix_entries[4];
+       struct ioat_dma_chan *idx[4];
 };
 
 /**
  * struct ioat_dma_chan - internal representation of a DMA channel
- * @device:
- * @reg_base:
- * @sw_in_use:
- * @completion:
- * @completion_low:
- * @completion_high:
- * @completed_cookie: last cookie seen completed on cleanup
- * @cookie: value of last cookie given to client
- * @last_completion:
- * @xfercap:
- * @desc_lock:
- * @free_desc:
- * @used_desc:
- * @resource:
- * @device_node:
  */
-
 struct ioat_dma_chan {
 
-       void *reg_base;
+       void __iomem *reg_base;
 
        dma_cookie_t completed_cookie;
        unsigned long last_completion;
+       unsigned long last_completion_time;
 
-       u32 xfercap;    /* XFERCAP register value expanded out */
+       size_t xfercap; /* XFERCAP register value expanded out */
 
        spinlock_t cleanup_lock;
        spinlock_t desc_lock;
        struct list_head free_desc;
        struct list_head used_desc;
+       unsigned long watchdog_completion;
+       int watchdog_tcp_cookie;
+       u32 watchdog_last_tcp_cookie;
+       struct delayed_work work;
 
        int pending;
+       int dmacount;
+       int desccount;
 
-       struct ioat_device *device;
+       struct ioatdma_device *device;
        struct dma_chan common;
 
        dma_addr_t completion_addr;
@@ -99,6 +106,8 @@ struct ioat_dma_chan {
                        u32 high;
                };
        } *completion_virt;
+       unsigned long last_compl_desc_addr_hw;
+       struct tasklet_struct cleanup_task;
 };
 
 /* wrapper around hardware descriptor format + additional software fields */
@@ -106,21 +115,51 @@ struct ioat_dma_chan {
 /**
  * struct ioat_desc_sw - wrapper around hardware descriptor
  * @hw: hardware DMA descriptor
- * @node:
- * @cookie:
- * @phys:
+ * @node: this descriptor will either be on the free list,
+ *     or attached to a transaction list (async_tx.tx_list)
+ * @tx_cnt: number of descriptors required to complete the transaction
+ * @async_tx: the generic software descriptor for all engines
  */
-
 struct ioat_desc_sw {
        struct ioat_dma_descriptor *hw;
        struct list_head node;
-       dma_cookie_t cookie;
-       dma_addr_t phys;
-       DECLARE_PCI_UNMAP_ADDR(src)
-       DECLARE_PCI_UNMAP_LEN(src_len)
-       DECLARE_PCI_UNMAP_ADDR(dst)
-       DECLARE_PCI_UNMAP_LEN(dst_len)
+       int tx_cnt;
+       size_t len;
+       dma_addr_t src;
+       dma_addr_t dst;
+       struct dma_async_tx_descriptor async_tx;
 };
 
-#endif /* IOATDMA_H */
+static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev)
+{
+       #ifdef CONFIG_NET_DMA
+       switch (dev->version) {
+       case IOAT_VER_1_2:
+               sysctl_tcp_dma_copybreak = 4096;
+               break;
+       case IOAT_VER_2_0:
+               sysctl_tcp_dma_copybreak = 2048;
+               break;
+       case IOAT_VER_3_0:
+               sysctl_tcp_dma_copybreak = 262144;
+               break;
+       }
+       #endif
+}
+
+#if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
+struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
+                                     void __iomem *iobase);
+void ioat_dma_remove(struct ioatdma_device *device);
+struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
+struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
+struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
+#else
+#define ioat_dma_probe(pdev, iobase)    NULL
+#define ioat_dma_remove(device)         do { } while (0)
+#define ioat_dca_init(pdev, iobase)    NULL
+#define ioat2_dca_init(pdev, iobase)   NULL
+#define ioat3_dca_init(pdev, iobase)   NULL
+#endif
 
+#endif /* IOATDMA_H */