sky2: dont enable PME legacy mode

[safe/jmp/linux-2.6] / drivers / char / hw_random / via-rng.c

diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index 0e786b6..794aacb 100644 (file)
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -11,7 +11,7 @@
  * derived from
  *
  * Hardware driver for the AMD 768 Random Number Generator (RNG)
- * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
+ * (c) Copyright 2001 Red Hat Inc
  *
  * derived from
  *
@@ -26,11 +26,12 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/pci.h>
 #include <linux/hw_random.h>
+#include <linux/delay.h>
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/cpufeature.h>
+#include <asm/i387.h>
 
 
 #define PFX    KBUILD_MODNAME ": "
@@ -42,6 +43,8 @@ enum {
        VIA_STRFILT_ENABLE      = (1 << 14),
        VIA_RAWBITS_ENABLE      = (1 << 13),
        VIA_RNG_ENABLE          = (1 << 6),
+       VIA_NOISESRC1           = (1 << 8),
+       VIA_NOISESRC2           = (1 << 9),
        VIA_XSTORE_CNT_MASK     = 0x0F,
 
        VIA_RNG_CHUNK_8         = 0x00, /* 64 rand bits, 64 stored bits */
@@ -65,23 +68,31 @@ enum {
  * Another possible performance boost may come from simply buffering
  * until we have 4 bytes, thus returning a u32 at a time,
  * instead of the current u8-at-a-time.
+ *
+ * Padlock instructions can generate a spurious DNA fault, so
+ * we have to call them in the context of irq_ts_save/restore()
  */
 
 static inline u32 xstore(u32 *addr, u32 edx_in)
 {
        u32 eax_out;
+       int ts_state;
+
+       ts_state = irq_ts_save();
 
        asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
                :"=m"(*addr), "=a"(eax_out)
                :"D"(addr), "d"(edx_in));
 
+       irq_ts_restore(ts_state);
        return eax_out;
 }
 
-static int via_rng_data_present(struct hwrng *rng)
+static int via_rng_data_present(struct hwrng *rng, int wait)
 {
        u32 bytes_out;
        u32 *via_rng_datum = (u32 *)(&rng->priv);
+       int i;
 
        /* We choose the recommended 1-byte-per-instruction RNG rate,
         * for greater randomness at the expense of speed.  Larger
@@ -96,12 +107,15 @@ static int via_rng_data_present(struct hwrng *rng)
         * completes.
         */
 
-       *via_rng_datum = 0; /* paranoia, not really necessary */
-       bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
-       bytes_out &= VIA_XSTORE_CNT_MASK;
-       if (bytes_out == 0)
-               return 0;
-       return 1;
+       for (i = 0; i < 20; i++) {
+               *via_rng_datum = 0; /* paranoia, not really necessary */
+               bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
+               bytes_out &= VIA_XSTORE_CNT_MASK;
+               if (bytes_out || !wait)
+                       break;
+               udelay(10);
+       }
+       return bytes_out ? 1 : 0;
 }
 
 static int via_rng_data_read(struct hwrng *rng, u32 *data)
@@ -115,8 +129,22 @@ static int via_rng_data_read(struct hwrng *rng, u32 *data)
 
 static int via_rng_init(struct hwrng *rng)
 {
+       struct cpuinfo_x86 *c = &cpu_data(0);
        u32 lo, hi, old_lo;
 
+       /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore.  The RNG
+        * is always enabled if CPUID rng_en is set.  There is no
+        * RNG configuration like it used to be the case in this
+        * register */
+       if ((c->x86 == 6) && (c->x86_model >= 0x0f)) {
+               if (!cpu_has_xstore_enabled) {
+                       printk(KERN_ERR PFX "can't enable hardware RNG "
+                               "if XSTORE is not enabled\n");
+                       return -ENODEV;
+               }
+               return 0;
+       }
+
        /* Control the RNG via MSR.  Tread lightly and pay very close
         * close attention to values written, as the reserved fields
         * are documented to be "undefined and unpredictable"; but it
@@ -130,6 +158,17 @@ static int via_rng_init(struct hwrng *rng)
        lo &= ~VIA_XSTORE_CNT_MASK;
        lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
        lo |= VIA_RNG_ENABLE;
+       lo |= VIA_NOISESRC1;
+
+       /* Enable secondary noise source on CPUs where it is present. */
+
+       /* Nehemiah stepping 8 and higher */
+       if ((c->x86_model == 9) && (c->x86_mask > 7))
+               lo |= VIA_NOISESRC2;
+
+       /* Esther */
+       if (c->x86_model >= 10)
+               lo |= VIA_NOISESRC2;
 
        if (lo != old_lo)
                wrmsr(MSR_VIA_RNG, lo, hi);
@@ -176,8 +215,8 @@ static void __exit mod_exit(void)
        hwrng_unregister(&via_rng);
 }
 
-subsys_initcall(mod_init);
+module_init(mod_init);
 module_exit(mod_exit);
 
-MODULE_DESCRIPTION("H/W RNG driver for VIA chipsets");
+MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
 MODULE_LICENSE("GPL");