/*
* pata_optidma.c - Opti DMA PATA for new ATA layer
* (C) 2006 Red Hat Inc
- * Alan Cox <alan@redhat.com>
*
* The Opti DMA controllers are related to the older PIO PCI controllers
* and indeed the VLB ones. The main differences are that the timing
#include <linux/libata.h>
#define DRV_NAME "pata_optidma"
-#define DRV_VERSION "0.2.1"
+#define DRV_VERSION "0.3.2"
enum {
READ_REG = 0, /* index of Read cycle timing register */
/**
* optidma_pre_reset - probe begin
- * @ap: ATA port
+ * @link: ATA link
+ * @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
-
-static int optidma_pre_reset(struct ata_port *ap)
+
+static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
{
+ struct ata_port *ap = link->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
- static const struct pci_bits optidma_enable_bits = {
+ static const struct pci_bits optidma_enable_bits = {
0x40, 1, 0x08, 0x00
};
- if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) {
- ata_port_disable(ap);
- printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
- return 0;
- }
- ap->cbl = ATA_CBL_PATA40;
- return ata_std_prereset(ap);
-}
-
-/**
- * optidma_probe_reset - probe reset
- * @ap: ATA port
- *
- * Perform the ATA probe and bus reset sequence plus specific handling
- * for this hardware. The Opti needs little handling - we have no UDMA66
- * capability that needs cable detection. All we must do is check the port
- * is enabled.
- */
+ if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
+ return -ENOENT;
-static void optidma_error_handler(struct ata_port *ap)
-{
- ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
+ return ata_sff_prereset(link, deadline);
}
/**
* Unlock the control register block for this adapter. Registers must not
* be unlocked in a situation where libata might look at them.
*/
-
+
static void optidma_unlock(struct ata_port *ap)
{
- unsigned long regio = ap->ioaddr.cmd_addr;
-
+ void __iomem *regio = ap->ioaddr.cmd_addr;
+
/* These 3 unlock the control register access */
- inw(regio + 1);
- inw(regio + 1);
- outb(3, regio + 2);
+ ioread16(regio + 1);
+ ioread16(regio + 1);
+ iowrite8(3, regio + 2);
}
/**
*
* Re-lock the configuration register settings.
*/
-
+
static void optidma_lock(struct ata_port *ap)
{
- unsigned long regio = ap->ioaddr.cmd_addr;
-
+ void __iomem *regio = ap->ioaddr.cmd_addr;
+
/* Relock */
- outb(0x83, regio + 2);
+ iowrite8(0x83, regio + 2);
}
/**
- * optidma_set_mode - set mode data
+ * optidma_mode_setup - set mode data
* @ap: ATA interface
* @adev: ATA device
* @mode: Mode to set
* IRQ here we depend on the host set locking to avoid catastrophe.
*/
-static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
+static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
struct ata_device *pair = ata_dev_pair(adev);
int pio = adev->pio_mode - XFER_PIO_0;
int dma = adev->dma_mode - XFER_MW_DMA_0;
- unsigned long regio = ap->ioaddr.cmd_addr;
+ void __iomem *regio = ap->ioaddr.cmd_addr;
u8 addr;
/* Address table precomputed with a DCLK of 2 */
/* Switch from IDE to control mode */
optidma_unlock(ap);
-
+
/*
* As with many controllers the address setup time is shared
addr = 0;
else
addr = addr_timing[pci_clock][pio];
-
+
if (pair) {
u8 pair_addr;
/* Hardware constraint */
if (pair_addr > addr)
addr = pair_addr;
}
-
+
/* Commence primary programming sequence */
/* First we load the device number into the timing select */
- outb(adev->devno, regio + MISC_REG);
+ iowrite8(adev->devno, regio + MISC_REG);
/* Now we load the data timings into read data/write data */
if (mode < XFER_MW_DMA_0) {
- outb(data_rec_timing[pci_clock][pio], regio + READ_REG);
- outb(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
+ iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
+ iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
} else if (mode < XFER_UDMA_0) {
- outb(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
- outb(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
+ iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
+ iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
}
/* Finally we load the address setup into the misc register */
- outb(addr | adev->devno, regio + MISC_REG);
+ iowrite8(addr | adev->devno, regio + MISC_REG);
/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
- outb(0x85, regio + CNTRL_REG);
-
+ iowrite8(0x85, regio + CNTRL_REG);
+
/* Switch back to IDE mode */
optidma_lock(ap);
-
+
/* Note: at this point our programming is incomplete. We are
not supposed to program PCI 0x43 "things we hacked onto the chip"
until we've done both sets of PIO/DMA timings */
}
/**
- * optiplus_set_mode - DMA setup for Firestar Plus
+ * optiplus_mode_setup - DMA setup for Firestar Plus
* @ap: ATA port
* @adev: device
* @mode: desired mode
* one
*/
-static void optiplus_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
+static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 udcfg;
int dev2 = 2 * adev->devno;
int unit = 2 * ap->port_no + adev->devno;
int udma = mode - XFER_UDMA_0;
-
+
pci_read_config_byte(pdev, 0x44, &udcfg);
if (mode <= XFER_UDMA_0) {
udcfg &= ~(1 << unit);
- optidma_set_mode(ap, adev, adev->dma_mode);
+ optidma_mode_setup(ap, adev, adev->dma_mode);
} else {
udcfg |= (1 << unit);
if (ap->port_no) {
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
- optidma_set_mode(ap, adev, adev->pio_mode);
+ optidma_mode_setup(ap, adev, adev->pio_mode);
}
/**
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
- optidma_set_mode(ap, adev, adev->dma_mode);
+ optidma_mode_setup(ap, adev, adev->dma_mode);
}
/**
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
- optiplus_set_mode(ap, adev, adev->pio_mode);
+ optiplus_mode_setup(ap, adev, adev->pio_mode);
}
/**
* DMA programming. The architecture of the Firestar makes it easier
* for us to have a common function so we provide wrappers
*/
-
+
static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
- optiplus_set_mode(ap, adev, adev->dma_mode);
+ optiplus_mode_setup(ap, adev, adev->dma_mode);
}
/**
* Turn the ATA device setup into PCI configuration bits
* for register 0x43 and return the two bits needed.
*/
-
+
static u8 optidma_make_bits43(struct ata_device *adev)
{
static const u8 bits43[5] = {
}
/**
- * optidma_post_set_mode - finalize PCI setup
- * @ap: port to set up
+ * optidma_set_mode - mode setup
+ * @link: link to set up
*
- * Finalise the configuration by writing the nibble of extra bits
- * of data into the chip.
+ * Use the standard setup to tune the chipset and then finalise the
+ * configuration by writing the nibble of extra bits of data into
+ * the chip.
*/
-
-static void optidma_post_set_mode(struct ata_port *ap)
+
+static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
{
+ struct ata_port *ap = link->ap;
u8 r;
int nybble = 4 * ap->port_no;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-
- pci_read_config_byte(pdev, 0x43, &r);
-
- r &= (0x0F << nybble);
- r |= (optidma_make_bits43(&ap->device[0]) +
- (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
-
- pci_write_config_byte(pdev, 0x43, r);
+ int rc = ata_do_set_mode(link, r_failed);
+ if (rc == 0) {
+ pci_read_config_byte(pdev, 0x43, &r);
+
+ r &= (0x0F << nybble);
+ r |= (optidma_make_bits43(&link->device[0]) +
+ (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
+ pci_write_config_byte(pdev, 0x43, r);
+ }
+ return rc;
}
static struct scsi_host_template optidma_sht = {
- .module = THIS_MODULE,
- .name = DRV_NAME,
- .ioctl = ata_scsi_ioctl,
- .queuecommand = ata_scsi_queuecmd,
- .can_queue = ATA_DEF_QUEUE,
- .this_id = ATA_SHT_THIS_ID,
- .sg_tablesize = LIBATA_MAX_PRD,
- .max_sectors = ATA_MAX_SECTORS,
- .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
- .emulated = ATA_SHT_EMULATED,
- .use_clustering = ATA_SHT_USE_CLUSTERING,
- .proc_name = DRV_NAME,
- .dma_boundary = ATA_DMA_BOUNDARY,
- .slave_configure = ata_scsi_slave_config,
- .bios_param = ata_std_bios_param,
+ ATA_BMDMA_SHT(DRV_NAME),
};
static struct ata_port_operations optidma_port_ops = {
- .port_disable = ata_port_disable,
+ .inherits = &ata_bmdma_port_ops,
+ .cable_detect = ata_cable_40wire,
.set_piomode = optidma_set_pio_mode,
.set_dmamode = optidma_set_dma_mode,
-
- .tf_load = ata_tf_load,
- .tf_read = ata_tf_read,
- .check_status = ata_check_status,
- .exec_command = ata_exec_command,
- .dev_select = ata_std_dev_select,
-
- .freeze = ata_bmdma_freeze,
- .thaw = ata_bmdma_thaw,
- .post_internal_cmd = ata_bmdma_post_internal_cmd,
- .error_handler = optidma_error_handler,
- .post_set_mode = optidma_post_set_mode,
-
- .bmdma_setup = ata_bmdma_setup,
- .bmdma_start = ata_bmdma_start,
- .bmdma_stop = ata_bmdma_stop,
- .bmdma_status = ata_bmdma_status,
-
- .qc_prep = ata_qc_prep,
- .qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
- .data_xfer = ata_pio_data_xfer,
-
- .irq_handler = ata_interrupt,
- .irq_clear = ata_bmdma_irq_clear,
-
- .port_start = ata_port_start,
- .port_stop = ata_port_stop,
- .host_stop = ata_host_stop
+ .set_mode = optidma_set_mode,
+ .prereset = optidma_pre_reset,
};
static struct ata_port_operations optiplus_port_ops = {
- .port_disable = ata_port_disable,
+ .inherits = &optidma_port_ops,
.set_piomode = optiplus_set_pio_mode,
.set_dmamode = optiplus_set_dma_mode,
-
- .tf_load = ata_tf_load,
- .tf_read = ata_tf_read,
- .check_status = ata_check_status,
- .exec_command = ata_exec_command,
- .dev_select = ata_std_dev_select,
-
- .freeze = ata_bmdma_freeze,
- .thaw = ata_bmdma_thaw,
- .post_internal_cmd = ata_bmdma_post_internal_cmd,
- .error_handler = optidma_error_handler,
- .post_set_mode = optidma_post_set_mode,
-
- .bmdma_setup = ata_bmdma_setup,
- .bmdma_start = ata_bmdma_start,
- .bmdma_stop = ata_bmdma_stop,
- .bmdma_status = ata_bmdma_status,
-
- .qc_prep = ata_qc_prep,
- .qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
- .data_xfer = ata_pio_data_xfer,
-
- .irq_handler = ata_interrupt,
- .irq_clear = ata_bmdma_irq_clear,
-
- .port_start = ata_port_start,
- .port_stop = ata_port_stop,
- .host_stop = ata_host_stop
};
/**
* optiplus_with_udma - Look for UDMA capable setup
* @pdev; ATA controller
*/
-
+
static int optiplus_with_udma(struct pci_dev *pdev)
{
u8 r;
int ret = 0;
int ioport = 0x22;
struct pci_dev *dev1;
-
+
/* Find function 1 */
dev1 = pci_get_device(0x1045, 0xC701, NULL);
- if(dev1 == NULL)
+ if (dev1 == NULL)
return 0;
-
+
/* Rev must be >= 0x10 */
pci_read_config_byte(dev1, 0x08, &r);
if (r < 0x10)
pci_read_config_byte(dev1, 0x52, &r);
if (r & 0x80) /* IDEDIR disabled */
ret = 1;
-done:
+done:
printk(KERN_WARNING "UDMA not supported in this configuration.\n");
done_nomsg: /* Wrong chip revision */
pci_dev_put(dev1);
static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
- static struct ata_port_info info_82c700 = {
- .sht = &optidma_sht,
- .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
+ static const struct ata_port_info info_82c700 = {
+ .flags = ATA_FLAG_SLAVE_POSS,
+ .pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
.port_ops = &optidma_port_ops
};
- static struct ata_port_info info_82c700_udma = {
- .sht = &optidma_sht,
- .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
- .udma_mask = 0x07,
+ static const struct ata_port_info info_82c700_udma = {
+ .flags = ATA_FLAG_SLAVE_POSS,
+ .pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
.port_ops = &optiplus_port_ops
};
- static struct ata_port_info *port_info[2];
- struct ata_port_info *info = &info_82c700;
+ const struct ata_port_info *ppi[] = { &info_82c700, NULL };
static int printed_version;
+ int rc;
if (!printed_version++)
dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
+ rc = pcim_enable_device(dev);
+ if (rc)
+ return rc;
+
/* Fixed location chipset magic */
inw(0x1F1);
inw(0x1F1);
pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
-
+
if (optiplus_with_udma(dev))
- info = &info_82c700_udma;
+ ppi[0] = &info_82c700_udma;
- port_info[0] = port_info[1] = info;
- return ata_pci_init_one(dev, port_info, 2);
+ return ata_pci_sff_init_one(dev, ppi, &optidma_sht, NULL);
}
static const struct pci_device_id optidma[] = {
- { PCI_DEVICE(0x1045, 0xD568), }, /* Opti 82C700 */
- { 0, },
+ { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
+
+ { },
};
static struct pci_driver optidma_pci_driver = {
- .name = DRV_NAME,
+ .name = DRV_NAME,
.id_table = optidma,
.probe = optidma_init_one,
- .remove = ata_pci_remove_one
+ .remove = ata_pci_remove_one,
+#ifdef CONFIG_PM
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+#endif
};
static int __init optidma_init(void)
return pci_register_driver(&optidma_pci_driver);
}
-
static void __exit optidma_exit(void)
{
pci_unregister_driver(&optidma_pci_driver);
}
-
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
MODULE_LICENSE("GPL");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff