Merge branch 'iommu-fixes-2.6.28' of git://git.kernel.org/pub/scm/linux/kernel/git...
[safe/jmp/linux-2.6] / arch / x86 / kernel / smpboot.c
index f84de2f..f71f96f 100644 (file)
@@ -282,6 +282,8 @@ static void __cpuinit smp_callin(void)
        cpu_set(cpuid, cpu_callin_map);
 }
 
+static int __cpuinitdata unsafe_smp;
+
 /*
  * Activate a secondary processor.
  */
@@ -292,9 +294,7 @@ static void __cpuinit start_secondary(void *unused)
         * fragile that we want to limit the things done here to the
         * most necessary things.
         */
-#ifdef CONFIG_VMI
        vmi_bringup();
-#endif
        cpu_init();
        preempt_disable();
        smp_callin();
@@ -397,7 +397,7 @@ static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
                                goto valid_k7;
 
                /* If we get here, not a certified SMP capable AMD system. */
-               add_taint(TAINT_UNSAFE_SMP);
+               unsafe_smp = 1;
        }
 
 valid_k7:
@@ -414,12 +414,10 @@ static void __cpuinit smp_checks(void)
         * Don't taint if we are running SMP kernel on a single non-MP
         * approved Athlon
         */
-       if (tainted & TAINT_UNSAFE_SMP) {
-               if (num_online_cpus())
-                       printk(KERN_INFO "WARNING: This combination of AMD"
-                               "processors is not suitable for SMP.\n");
-               else
-                       tainted &= ~TAINT_UNSAFE_SMP;
+       if (unsafe_smp && num_online_cpus() > 1) {
+               printk(KERN_INFO "WARNING: This combination of AMD"
+                       "processors is not suitable for SMP.\n");
+               add_taint(TAINT_UNSAFE_SMP);
        }
 }
 
@@ -893,9 +891,11 @@ do_rest:
                smpboot_setup_warm_reset_vector(start_ip);
                /*
                 * Be paranoid about clearing APIC errors.
-               */
-               apic_write(APIC_ESR, 0);
-               apic_read(APIC_ESR);
+               */
+               if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
+                       apic_write(APIC_ESR, 0);
+                       apic_read(APIC_ESR);
+               }
        }
 
        /*