x86: Centaur Isaiah processor to use sysenter in 64-bit compatibility mode rather...

[safe/jmp/linux-2.6] / arch / x86 / kernel / setup_64.c

diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index c6fe1e4..b803007 100644 (file)
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -58,7 +58,6 @@
 #include <asm/mmu_context.h>
 #include <asm/proto.h>
 #include <asm/setup.h>
-#include <asm/mach_apic.h>
 #include <asm/numa.h>
 #include <asm/sections.h>
 #include <asm/dmi.h>
@@ -67,6 +66,7 @@
 #include <asm/ds.h>
 #include <asm/topology.h>
 
+#include <mach_apic.h>
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
@@ -347,7 +347,7 @@ void __init setup_arch(char **cmdline_p)
 
        check_efer();
 
-       init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
+       max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
        if (efi_enabled)
                efi_init();
 
@@ -729,6 +729,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 
        if (amd_apic_timer_broken())
                disable_apic_timer = 1;
+
+       if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
+               unsigned long long tseg;
+
+               /*
+                * Split up direct mapping around the TSEG SMM area.
+                * Don't do it for gbpages because there seems very little
+                * benefit in doing so.
+                */
+               if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
+               (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
+                       set_memory_4k((unsigned long)__va(tseg), 1);
+       }
 }
 
 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
@@ -872,6 +885,32 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
        srat_detect_node();
 }
 
+static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
+{
+       if (c->x86 == 0x6 && c->x86_model >= 0xf)
+               set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+}
+
+static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
+{
+       /* Cache sizes */
+       unsigned n;
+
+       n = c->extended_cpuid_level;
+       if (n >= 0x80000008) {
+               unsigned eax = cpuid_eax(0x80000008);
+               c->x86_virt_bits = (eax >> 8) & 0xff;
+               c->x86_phys_bits = eax & 0xff;
+       }
+
+       if (c->x86 == 0x6 && c->x86_model >= 0xf) {
+               c->x86_cache_alignment = c->x86_clflush_size * 2;
+               set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+               set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+       }
+       set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+}
+
 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 {
        char *v = c->x86_vendor_id;
@@ -880,6 +919,8 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
                c->x86_vendor = X86_VENDOR_AMD;
        else if (!strcmp(v, "GenuineIntel"))
                c->x86_vendor = X86_VENDOR_INTEL;
+       else if (!strcmp(v, "CentaurHauls"))
+               c->x86_vendor = X86_VENDOR_CENTAUR;
        else
                c->x86_vendor = X86_VENDOR_UNKNOWN;
 }
@@ -976,6 +1017,9 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
                if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
                        set_cpu_cap(c, X86_FEATURE_PAT);
                break;
+       case X86_VENDOR_CENTAUR:
+               early_init_centaur(c);
+               break;
        }
 
 }
@@ -1012,6 +1056,10 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                init_intel(c);
                break;
 
+       case X86_VENDOR_CENTAUR:
+               init_centaur(c);
+               break;
+
        case X86_VENDOR_UNKNOWN:
        default:
                display_cacheinfo(c);